Partial Array Density Memory Security via Disabled Row Buffers
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Solution Overview
Problem
As memory cell density increases, the power consumption for refreshing memory cells also rises, and row disturb attacks can lead to data degradation, with existing methods either increasing power usage or inadvertently turning memory rows into aggressors, compromising data security and retention.
Innovation Solution
Implementing partial array density (PAD) secure regions where less than all memory rows are enabled to store data, with disabled rows acting as a buffer to reduce row disturb effects and using distinct refresh protocols for PAD secure regions to conserve power and enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage capacity is improved, but power consumption for refreshing memory cells increases
Solution Approach 1:
The memory array is segmented into secure regions with disabled memory rows interspersed among enabled rows. This segmentation creates physical separation that reduces row disturb effects, allowing the system to maintain security and data integrity while managing refresh power consumption more effectively in high-density configurations.
Solution Approach 2:
Disabled memory rows act as intermediary buffer zones between enabled memory rows. These intermediary rows absorb or mitigate the row disturb effects that would otherwise directly impact adjacent enabled rows, reducing the frequency and power consumption of refresh operations needed to maintain data integrity.
2Reliability
If refresh operations are performed more frequently, then data retention is improved, but power consumption increases
Solution Approach 1:
Disabled memory rows are pre-configured as buffer zones before any row disturb attacks or refresh operations occur. This preliminary structural arrangement proactively mitigates row disturb effects, reducing the need for frequent refresh operations and thereby lowering power consumption while maintaining data retention.
Solution Approach 2:
The disabled memory rows, which represent lost storage capacity, are converted into beneficial buffer zones that protect enabled rows from row disturb attacks. This transformation turns a potential disadvantage (reduced density) into a security and power efficiency advantage by reducing refresh requirements.
3Quantity of substance
If all memory rows are enabled to store data, then storage density is maximized, but row disturb attacks can compromise data security
Solution Approach 1:
The memory array is divided into enabled and disabled rows, creating segmented zones where disabled rows serve as protective barriers. This segmentation physically separates enabled rows that store sensitive data, making row disturb attacks less effective while maintaining overall system security.
Solution Approach 2:
Disabled memory rows function as intermediary protective layers between potential attack vectors and the enabled rows containing valuable data. These intermediary rows absorb or deflect row disturb effects, protecting the security and integrity of data stored in enabled rows.
Data Source
AI summary
Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.