Single-Ended Sense Amplifier Circuit Low Voltage Operation
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Solution Overview
Problem
Conventional charge transfer type sense amplifier circuits face difficulties in achieving sufficient operating margin during low voltage operation, especially when using memory cells with small capacitance, as the amplifying operation is hindered due to increased capacitance at the sense node and reduced voltage difference.
Innovation Solution
A single-ended sense amplifier circuit is employed, which controls the amplifying operation in a charge distributing mode by setting appropriate voltages for the bit line and sense node, reducing capacitance at the sense node and allowing for sufficient voltage difference between high and low level data, thereby improving operating margin, especially at low voltage operations of about 1V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large-scale latch type differential amplifier is employed in a conventional charge transfer type sense amplifier circuit, then the amplifying operation can be achieved at relatively high power supply voltages (3V or 2V), but the capacitance at the sense node increases significantly, which hinders the amplifying operation at low power supply voltages (1V) and reduces the voltage difference between high and low level data
Solution Approach 1:
The patent extracts and removes the large-scale latch type differential amplifier from the conventional charge transfer type sense amplifier circuit, replacing it with a simpler single-ended sense amplifier circuit. This extraction eliminates the excessive capacitance at the sense node while maintaining the essential amplifying function, thereby resolving the contradiction between amplifying operation reliability and device complexity.
Solution Approach 2:
The patent changes the operational parameters by controlling the sense amplifier circuit to operate in charge distributing mode instead of charge transfer mode. This parameter change allows the circuit to achieve sufficient voltage difference at the sense node even with reduced capacitance, enabling reliable operation at low power supply voltages while minimizing the capacitance increase that would otherwise occur.
2Use of energy by moving object
If the power supply voltage is lowered to 1V to reduce power consumption, then energy efficiency is improved, but the voltage difference at the sense node becomes reduced and sufficient operating margin cannot be obtained
Solution Approach 1:
The patent changes the operational mode parameter from charge transfer to charge distributing mode, which fundamentally alters how the sense amplifier processes signals. This parameter change enables the circuit to maintain sufficient voltage difference and operating margin at low power supply voltages (1V) by distributing charge more effectively across the capacitances, thereby achieving both low power consumption and reliable operation.
Solution Approach 2:
The patent applies local quality by optimizing the voltage distribution at specific nodes (bit line and sense node) through controlled charging and discharging processes. By locally controlling the voltage at the sense node to achieve sufficient difference from the bit line voltage, the circuit maintains adequate operating margin even at reduced power supply voltages, thus resolving the contradiction between power consumption and operational reliability.
3Area of stationary object
If memory cells with small capacitance are used to achieve miniaturization, then the memory cell size is reduced, but the voltage difference in reading out high and low level data becomes reduced, making it difficult to obtain sufficient operating margin
Solution Approach 1:
The patent changes the sense amplifier's operational parameters by controlling it to operate in charge distributing mode with specific voltage settings at the bit line and sense node. This parameter change enables the circuit to amplify the voltage difference generated by small capacitance memory cells effectively, maintaining sufficient operating margin even when the memory cell capacitance is reduced for miniaturization.
Solution Approach 2:
The patent applies local quality by optimizing the voltage distribution and signal characteristics at the sense node and bit line locally. Through controlled charging and discharging processes, the circuit enhances the local voltage difference at the sense node, compensating for the reduced capacitance of miniaturized memory cells and thereby maintaining reliable operation with smaller memory cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-ended sense amplifier circuit achieves a sufficient operating margin in low voltage operations, even with memory cells having small capacitance, and reduces the area of local sense amplifiers, enhancing reliability and production yield while allowing for a smaller chip area.
Implementation Method 1
the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor
Implementation Method 2
the voltage difference at the sense node Ns in reading out high and low level data from the memory cell MC becomes reduced
Data Source
AI summary
A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor having a gate connected to the sense node amplifies a signal transmitted from the bit line via the first MOS transistor. The first voltage setting circuit sets the bit line to a first voltage, and the second voltage setting circuit sets the sense node to a second voltage. In the sense amplifier circuit, after setting the bit line and the sense node to respective voltages, the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor.