Hub Device Firmware Initialization via Shared Memory
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Solution Overview
Problem
Hub devices face limitations in port extension and manufacturing costs due to the need for multiple external memory devices and dedicated configurations for each chip, which restricts their efficiency and scalability.
Innovation Solution
A hub device architecture that shares a single external memory device among multiple chips, enabling tiered hub configurations where downstream ports of one chip are connected to upstream ports of another, allowing sequential initialization and reducing manufacturing costs by eliminating the need for dedicated memory devices for each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each chip has its own dedicated external memory device, then firmware loading is reliable and simple, but manufacturing cost increases and device complexity increases
Solution Approach 1:
Multiple chips share a single external memory device instead of each chip having its own dedicated memory. The memory is configured to be accessible by multiple chips through a shared bus interface, reducing the total number of memory devices required while maintaining firmware loading capability for all chips.
Solution Approach 2:
The external memory device serves multiple functions by providing firmware storage for multiple different chips. A single memory device is designed to be universally accessible by various chips in the tiered hub configuration, eliminating the need for dedicated memory devices for each chip type.
2Productivity
If multiple external memory devices are used for each chip, then firmware access is fast and concurrent, but manufacturing cost increases
Solution Approach 1:
Multiple chips share a single external memory device through a common bus interface, reducing the total component count and manufacturing cost. The shared memory architecture consolidates what would otherwise require multiple separate memory devices, one for each chip.
3Loss of time
If chips are initialized simultaneously, then system startup is fast, but memory access collisions occur
Solution Approach 1:
The system implements a preliminary initialization sequence where chips are started up in a predetermined order rather than simultaneously. The first chip is initialized before subsequent chips, ensuring that memory access conflicts are avoided while maintaining an efficient startup process.
Solution Approach 2:
Chips are initialized in periodic stages rather than all at once. The initialization process is divided into sequential phases where each chip is activated and initialized in turn, preventing memory access collisions while completing the overall startup sequence efficiently.
Data Source
AI summary
A hub device and corresponding method include a first chip having at least a first upstream port and a plurality of first downstream ports, a second chip, having at least a second upstream port and at least one second downstream port; and an external memory device, storing firmware data corresponding to the first chip and the second chip. One one of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub, and the first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.