DRAM Word Line Voltage Control for Speed Retention Trade-off

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Solution Overview

Problem

Conventional DRAM technologies cannot arbitrarily set data retention and operation speed, leading to inefficiencies in memory hierarchical structures and increased overhead during data transmission between memories with different retention characteristics.

Innovation Solution

A semiconductor memory device with a hierarchical structure that includes a first and second memory region, where the data retention and operation speed can be arbitrarily set by controlling the voltage supplied to the word lines, allowing for flexible use of DRAM as a working memory or storage, similar to SRAM or NAND flash memory, by using a controller to manage voltage settings and refresh cycles based on retention information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional DRAM is used with fixed operation parameters, then manufacturing and control are simplified, but data retention and operation speed cannot be arbitrarily set, limiting adaptability in memory hierarchical structures

Engineering Contradiction:

Improvedata retention and operation speed settingsVSAvoidvoltage control circuitry and operation modes

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic voltage control of word lines to enable DRAM to operate in multiple modes (high-speed mode with higher voltage and low-retention mode with lower voltage). The word line voltage is dynamically adjusted based on the desired operation mode, allowing the same DRAM device to adapt to different data retention requirements without changing the physical structure.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of DRAM by controlling the voltage level of word lines during sleep mode. By setting the word line voltage to a first level (higher) for high-speed operation or a second level (lower) for high-retention operation, the patent enables arbitrary setting of data retention and operation speed, directly resolving the adaptability limitation of conventional DRAM.

Inventive Principle:

Principle #35Parameter changes

2Speed

If DRAM operates in high-speed mode with higher word line voltage, then operation speed improves, but data retention during sleep mode decreases

Engineering Contradiction:

Improveoperation speedVSAvoiddata retention during sleep mode

Core Design Contradiction:

SpeedVSDuration of action of stationary object

Solution Approach 1:

The patent dynamically adjusts the word line voltage level during sleep mode based on the desired performance characteristic. When high operation speed is needed, the word line voltage is set to a higher first level during active operations. When high data retention is needed, the word line voltage is set to a lower second level during sleep mode, enabling flexible trade-off between speed and retention.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent directly controls the word line voltage parameter to achieve different operation modes. By setting the voltage to a first level (V1) for high-speed mode or a second level (V2) for high-retention mode, the patent enables arbitrary adjustment of the speed-retention trade-off, allowing optimization based on specific application requirements.

Inventive Principle:

Principle #35Parameter changes

3Duration of action of stationary object

If DRAM operates in high-retention mode with lower word line voltage, then data retention improves, but operation speed decreases

Engineering Contradiction:

Improvedata retention during sleep modeVSAvoidoperation speed

Core Design Contradiction:

Duration of action of stationary objectVSSpeed

Solution Approach 1:

The patent changes the word line voltage parameter to a lower second level when high data retention is required. This lower voltage reduces leakage current during sleep mode, improving data retention. The same DRAM device can later switch to a higher first voltage level when high operation speed is needed, providing flexible adaptation to different performance requirements.

Inventive Principle:

Principle #35Parameter changes

4Adaptability or versatility

If memory hierarchical structure uses multiple memory types (SRAM, DRAM, NAND flash), then different data retention requirements are met, but overhead increases during data transmission between memories

Engineering Contradiction:

Improvedata retention coverage rangeVSAvoidoverhead during data transmission

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent makes DRAM a universal memory that can replace SRAM, DRAM, and NAND flash by controlling word line voltage. When voltage is set to the first level, DRAM operates with high-speed characteristics suitable for working memory. When voltage is set to the second level, DRAM operates with high-retention characteristics suitable for storage memory. This eliminates the need for multiple memory types and reduces data transmission overhead.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10332581B2Semiconductor memory device

Publication Date: 2019.06.25 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.