SRAM Write Assist Circuit with Back-Gate Control
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Solution Overview
Problem
As semiconductor technology scales down, random dopant fluctuation, line edge roughness, and short channel effects lead to increased threshold voltage fluctuations in SRAM cells, making it challenging to achieve sufficient yield and stability in small-geometry devices like 22 nm technology, especially with planar bulk MOSFETs, and existing read- and write-assist circuits often compromise performance by increasing leakage current and power consumption.
Innovation Solution
The proposed solution involves a static memory cell design with a write-assist circuit that combines back-gate and ground voltage control, where the back-gate node of NMOS transistors is tied to the ground voltage node, reducing leakage current and improving word-line write trip voltage without significant degradation in read static noise margin, by forming a common node with the source nodes of pull-down transistors and pass-gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar bulk MOSFETs are used for high integration density, then transistor integration is improved, but threshold voltage stability and write ability deteriorate due to random dopant fluctuation and short channel effects
Solution Approach 1:
The patent changes the physical parameters of the MOSFET by transitioning from planar bulk to ETSOI structure with thin BOX layer, enabling back-gate voltage control to adjust threshold voltage and improve stability while maintaining high integration density
Solution Approach 2:
The patent introduces a third dimension by adding back-gate control to the traditional planar MOSFET structure, allowing independent control of threshold voltage through back-gate voltage without affecting the planar integration layout
2Reliability
If forward body bias is applied to control threshold voltage in ETSOI devices, then threshold voltage control is improved, but leakage current increases due to p-n junction leakage
Solution Approach 1:
The patent converts the harmful p-n junction leakage effect into a beneficial mechanism by applying reverse back-gate bias during read operations, which strengthens the depletion region and reduces leakage current while maintaining threshold voltage control capability
Solution Approach 2:
The patent dynamically adjusts the back-gate voltage based on operation mode: applying reverse bias during read to reduce leakage, and forward bias during write to improve write ability, thereby optimizing performance for different operational states
3Reliability
If read-assist circuits are used to improve read stability, then read static noise margin is improved, but write ability deteriorates due to increased leakage current and power consumption
Solution Approach 1:
The patent segments the assist circuit functionality into separate back-gate control nodes for different transistor groups, allowing independent optimization of read stability and write ability without mutual interference
Solution Approach 2:
The back-gate control mechanism serves multiple functions: improving read stability through noise margin enhancement, improving write ability through threshold voltage adjustment, and reducing leakage current through reverse bias, replacing multiple separate assist circuits with a unified control approach
4Reliability
If write-assist circuits are used to improve write ability, then word-line write trip voltage is improved, but read stability deteriorates due to increased power consumption
Solution Approach 1:
The patent applies periodic back-gate voltage pulses during write operations to temporarily enhance write ability, then returns to normal operating voltage to maintain read stability, thereby achieving write assistance without continuous power consumption
Data Source
AI summary
Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.