Semiconductor Reference Column Using Resistive Memory Cells
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Solution Overview
Problem
Existing memory circuits face challenges in generating a precise reference current efficiently, leading to increased area requirements for memory cells used in generating this current, which complicates data reading operations.
Innovation Solution
The implementation of a reference column with resistive memory cells at its ends, where data of different states is stored, allowing current paths to be formed only through these cells during read operations, enabling the generation of a precise reference current using a single reference column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple reference columns are used to generate reference current, then the precision of reference current is improved, but the area occupied by memory cells is increased
Solution Approach 1:
The patent merges the functions of multiple reference columns into a single reference column by having both first and second bit lines connect to the same reference column. This allows the single reference column to serve multiple purposes and generate reference current for multiple normal columns, thereby reducing the total area while maintaining reference current precision.
Solution Approach 2:
The reference column is designed with multi-functionality to serve multiple normal columns simultaneously. By connecting multiple bit lines to a single reference column and using select lines to control which normal columns are accessed, the reference column becomes a universal component that can generate reference current for different memory cells as needed, reducing the need for dedicated reference columns for each normal column.
2Measurement precision
If multiple reference columns are used to generate reference current, then the reference current precision is improved, but the circuit complexity is increased
Solution Approach 1:
The patent combines multiple reference column functions into a single reference column structure, reducing the number of separate circuit paths and components. This merging approach simplifies the overall circuit architecture while maintaining the ability to generate precise reference current through controlled selection of memory cell states.
Solution Approach 2:
The patent introduces dynamic control through select lines (first select line and second select line) that can dynamically enable or disable connections between bit lines and the reference column. This dynamic switching capability allows the same hardware structure to serve multiple functions at different times, reducing circuit complexity while maintaining precision.
3Area of stationary object
If resistive memory cells are used to generate reference current, then the area is reduced, but the manufacturing precision requirements are increased
Solution Approach 1:
The patent changes the operational parameters of resistive memory cells by utilizing their resistance state characteristics to generate reference current. By programming specific memory cells to be in high-resistance or low-resistance states and connecting them in parallel, the system generates precise reference currents without requiring additional dedicated reference columns, thereby reducing area while managing manufacturing precision through parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area required for memory cells generating the reference current, improving data reading efficiency and reducing circuit complexity.
Implementation Method 1
each of the first to Nth resistive memory cells may include: a resistance variable element configured to be changed in its resistance value according to a logic value of data stored therein
Data Source
AI summary
A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of a second state is stored in the Nth resistive memory cell before a read operation, and the first and Nth resistive memory cells form current paths between the reference bit line and the reference source line in the read operation.