STT-MRAM Bit Error Rate Management via Adaptive Pulse Width
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Solution Overview
Problem
Spin transfer torque magnetoresistive random-access memory (STT-MRAM) technologies face challenges in achieving reliable write operations while balancing write pulse width, energy consumption, and latency, as longer write pulses improve reliability but increase latency and energy use.
Innovation Solution
A method and apparatus that determine and store performance characteristics relating bit error rate to programming pulse width, temperature, history-based predictive parameters, and coding schemes, allowing for adaptive adjustments in write operations to manage STT-MRAM memory, including varying pulse widths and coding to optimize reliability and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write pulse width is increased to improve write reliability, then the bit error rate decreases, but the write latency and energy consumption increase
Solution Approach 1:
The patent applies dynamics by making the write pulse width adjustable rather than fixed. The system dynamically selects between long and short write operations based on real-time conditions such as temperature and desired bit error rate thresholds, allowing optimization of both reliability and latency for different operating scenarios
Solution Approach 2:
The patent changes the parameter of write pulse width based on temperature conditions and target bit error rates. By storing and utilizing bit error rate relationship information that correlates temperature with optimal pulse widths, the system adapts parameters to maintain reliability while minimizing latency
2Reliability
If the write pulse width is increased to improve write reliability, then the bit error rate decreases, but the energy consumption increases
Solution Approach 1:
The system dynamically adjusts energy consumption by selecting appropriate write pulse widths based on temperature and reliability requirements. Rather than always using long pulses that consume more energy, the system adapts to current conditions, reducing energy usage when short writes suffice
Solution Approach 2:
The patent changes operational parameters including write pulse width and coding scheme based on temperature and desired bit error rate. This allows the system to optimize energy consumption by using minimal necessary resources to achieve the required reliability level
3Use of energy by moving object
If adaptive write operations are implemented to reduce latency and energy consumption, then power efficiency improves, but the device complexity increases
Solution Approach 1:
The patent implements self-service by having the memory device determine and store its own bit error rate relationship information internally. The memory autonomously selects appropriate write operations based on temperature and stored characteristics, eliminating the need for complex external controller logic
Solution Approach 2:
The patent uses stored bit error rate relationship information as an intermediary that bridges temperature conditions and optimal write parameters. This pre-stored lookup information simplifies the decision-making process, avoiding complex real-time calculations while achieving adaptive optimization
Data Source
AI summary
Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.