Stacked Transistor Memory Cell Area Reduction
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Solution Overview
Problem
As memory devices, such as DRAM, are miniaturized, it becomes challenging to maintain sufficient capacitance in capacitors, leading to area constraints and inefficiencies in 1T1C configurations, while 2T0C configurations occupy more space due to the need for separate transistors and capacitors.
Innovation Solution
A memory device design featuring stacked transistors in a 2T0C configuration, where read and write transistors are vertically aligned, sharing a common gate dielectric and gate conductor, and utilizing a capacitance-free architecture where gate capacitance serves as the memory element, with conductive lines intersecting to form memory cells, allowing for self-aligned and area-efficient construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor size is reduced to miniaturize memory device, then device area is reduced, but capacitance becomes insufficient to hold data
Solution Approach 1:
The patent extracts the capacitor component entirely from the memory cell structure, transitioning from a 1T1C configuration to a 2T0C configuration. The gate capacitance of the read transistor is utilized instead of a separate capacitor, eliminating the capacitance area constraint while maintaining data storage capability.
Solution Approach 2:
The read transistor's gate structure serves dual functions: as the control element for reading operations and as the memory element for data storage. This multi-functionality eliminates the need for a dedicated capacitor, resolving the contradiction between area reduction and capacitance maintenance.
2Reliability
If 2T0C configuration is used to eliminate capacitor, then capacitance issue is resolved, but device area increases due to separate transistors
Solution Approach 1:
The patent transitions from a planar arrangement of transistors to a vertical stacked configuration. The read transistor and write transistor are stacked in the vertical dimension, allowing both transistors to share the same footprint area and reducing the overall device area despite the increased transistor count.
Solution Approach 2:
The patent merges the read transistor and write transistor into a single vertical stack, sharing common structures such as the active region and gate electrodes. This combining approach reduces redundant structures and minimizes the total area occupied by the memory cell.
3Area of moving object
If transistors are stacked vertically to save area, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms the active region and gate structures in a predetermined sequence before final transistor definition. The gate electrodes are formed to extend through the stack, and isolation structures are prepared in advance, simplifying subsequent processing steps and reducing manufacturing complexity despite the vertical stacking architecture.
Data Source
AI summary
Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction, and adjacent connection line layers respectively include conductive lines extending in directions intersected; a plurality of memory cells respectively including first and second transistors stacked. A first active layer of the first transistor includes first and second source/drain regions respectively electrically connected with conductive lines in the first and second connection line layers. A second active layer of the second transistor includes a first source/drain region electrically connected with a gate conductor layer of the first transistor, and a second source/drain region electrically connected with a conductive line in the third connection line layer. A gate conductor layer of the second transistor of each memory cell is electrically connected to a conductive line in the fourth connection line layer.