Wordline Tracking Circuit with Pre-Charge Control
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Solution Overview
Problem
In high-density semiconductor memories, the long wordline resistance and capacitance cause performance limitations and reliability issues due to increased RC delays, especially as technology advances, leading to degraded read/write margins and potential malfunctions.
Innovation Solution
A wordline tracking circuit is introduced, which includes a tracking wordline and a tracking bitline pre-charge circuit with a pull-up component and a cut-off component, allowing for pre-charging of the tracking bitline using the near-end wordline pulse's falling edge and interrupting current paths to prevent crowbar currents, thereby reducing the impact of wordline impedance on pulse degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wordline length is increased to support high-density memory, then memory capacity is improved, but RC delay increases causing performance degradation
Solution Approach 1:
The patent divides the long wordline into multiple segments by inserting intermediate buffer stages along the wordline. These buffers refresh and re-drive the signal at intermediate points, effectively breaking the long RC delay path into shorter segments, thereby reducing overall signal degradation while maintaining support for high-density memory arrays.
Solution Approach 2:
The patent introduces intermediate buffer circuits as mediator elements between the wordline driver and the far-end memory cells. These buffers act as signal regeneration points that compensate for RC delay effects, ensuring signal integrity is maintained across the extended wordline length required for high capacity memory.
2Quantity of substance
If wordline resistance increases due to technology scaling, then transistor density is improved, but read/write margin degrades
Solution Approach 1:
The patent applies different design optimizations to different regions of the wordline. Intermediate buffers are strategically placed at locations where signal degradation becomes significant, providing localized signal regeneration. Additionally, the buffer strength and sizing are optimized based on their position along the wordline to compensate for varying resistance effects in different regions.
Solution Approach 2:
The patent adjusts critical parameters such as buffer transistor sizing, threshold voltages, and operating voltages to optimize performance. By changing these parameters, the buffers can effectively compensate for the increased wordline resistance caused by technology scaling, maintaining adequate read/write margins despite higher resistance values.
3Loss of time
If wordline pulse width is reduced due to increased slew time, then RC delay effect is minimized, but effective pulse width for reliable operation decreases
Solution Approach 1:
The intermediate buffers are designed to anticipate and compensate for signal degradation before it becomes critical. By placing buffers at strategically determined intervals, the signal is refreshed in advance before excessive slew time accumulates, ensuring that the effective pulse width remains sufficient for reliable memory cell operation throughout the entire wordline length.
Data Source
AI summary
A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.