DRAM Row Hammer Mitigation via Selective Target Refresh
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Solution Overview
Problem
Current solutions for mitigating row hammering attacks in DRAM memory, such as doubling the refresh rate or implementing Target Row Refresh (TRR) circuits, are either power-intensive, complex, or inefficient, and do not effectively handle the vulnerability of DRAM integrated circuits to data disturb errors without significant overhead or system burden.
Innovation Solution
A DRAM integrated circuit design that incorporates a global TRR path with a two-stage filtering system using a FIFO CAM and a BBR CAM to monitor and filter row addresses, tracking only frequently accessed rows and performing additional refresh cycles only when necessary, thereby reducing power consumption and system complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate is doubled to mitigate row hammering attacks, then data security is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements selective refresh by identifying specific target rows that are frequently accessed and only refreshing those rows and their adjacent victim rows, rather than refreshing the entire memory array. This local approach maintains data security for vulnerable rows while significantly reducing overall power consumption compared to global refresh strategies.
Solution Approach 2:
The system proactively identifies target rows before row hammering attacks can cause data loss by monitoring access patterns and predicting which rows are likely to be targeted. Refresh operations are performed in advance on these identified rows and their adjacent victims, preventing potential data disturbs while avoiding unnecessary refreshes on non-vulnerable rows.
2Reliability
If Target Row Refresh (TRR) circuits are implemented to mitigate row hammering, then data security is improved, but device complexity increases
Solution Approach 1:
The patent introduces a row address filter as an intermediary component that sits between the memory controller and the refresh circuitry. This filter monitors row access patterns, identifies target rows, and selectively enables refresh operations only when needed. The intermediary approach simplifies the overall system by avoiding complex dedicated TRR circuits while maintaining effective row hammering mitigation.
3Reliability
If frequent refresh cycles are performed to prevent row disturbs, then data reliability is improved, but system performance deteriorates
Solution Approach 1:
The patent applies partial refresh action by performing refresh operations only on a subset of rows that are identified as vulnerable to row hammering attacks, rather than refreshing all rows in the memory array. This selective approach maintains data reliability for critical rows while minimizing the performance overhead associated with frequent refresh cycles.
4Measurement precision
If comprehensive row monitoring is implemented to detect row hammering attacks, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the row monitoring function into a simplified filter mechanism that tracks only the most critical parameters (row access frequency and patterns) rather than comprehensively monitoring all possible attack vectors. This segmented approach provides sufficient detection accuracy for row hammering attacks while keeping the monitoring complexity manageable through focused, selective tracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates row hammering attacks with minimal overhead, reducing the need for frequent refresh cycles and maintaining system performance, while being transparent to the memory controller and operating system.
Implementation Method 1
data is stored by capturing a quantity of charge on a capacitor in each memory cell
Implementation Method 2
the capacitive coupling between adjacent word lines is increased
Data Source
AI summary
The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.