Hybrid TFFE VFFE Equalization for GDDR6 Transmitter ISI Jitter

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Solution Overview

Problem

High-speed memory interface transmitters face challenges in effectively equalizing data signals at 24 Gbps speeds due to high Inter Symbol Interference (ISI) jitter, with existing techniques like pre-emphasis, de-emphasis, and Time-Feed Forward Equalization (TFFE) either degrading signal integrity, increasing power noise, or having limited coefficient settings, making them unsuitable for high-speed transmitters using GDDR6 DRAM.

Innovation Solution

A hybrid equalization technique combining Time-Feed Forward Equalization (TFFE) and Voltage-Feed Forward Equalization (VFFE) to address both driver stage and intermediate data path ISI jitter, eliminating the shortcomings of individual techniques by using TFFE for internal data path equalization and VFFE for driver-stage equalization, thereby reducing PSI jitter and achieving stable operation at 24 Gbps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-emphasis equalization is used to reduce ISI jitter at the driver stage, then ISI jitter is reduced, but signal integrity degrades due to changed output driver impedance

Engineering Contradiction:
ImproveISI jitter reductionVSAvoidsignal integrity degradation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The equalization function is segmented into two distinct parts: TFFE handles the internal data path ISI jitter, while VFFE handles the driver stage ISI jitter. This segmentation allows each equalization technique to operate in its optimal domain without the harmful side effects of the other, resolving the contradiction between ISI reduction and signal integrity maintenance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary hybrid equalization structure that combines TFFE and VFFE circuits. The TFFE circuit processes data before the driver stage, and the VFFE circuit provides additional equalization at the driver output, acting as a mediator that achieves comprehensive ISI reduction without compromising signal integrity through impedance changes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If pre-emphasis equalization is used to reduce ISI jitter, then ISI jitter is reduced, but Power Supply Induced (PSI) jitter increases due to increased switching current

Engineering Contradiction:
ImproveISI jitter reductionVSAvoidPSI jitter increase
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The equalization function is segmented into two distinct parts: TFFE handles the internal data path ISI jitter, while VFFE handles the driver stage ISI jitter. This segmentation allows each equalization technique to operate in its optimal domain without the harmful side effects of the other, resolving the contradiction between ISI reduction and signal integrity maintenance.

Inventive Principle:
Principle #1Segmentation

3Reliability

If TFFE is used to equalize internal data path ISI jitter, then internal data path ISI is reduced, but the unit interval becomes very small resulting in narrow time margin

Engineering Contradiction:
Improveinternal data path ISI reductionVSAvoidnarrow time margin
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The equalization function is segmented into two distinct parts: TFFE handles the internal data path ISI jitter, while VFFE handles the driver stage ISI jitter. This segmentation allows each equalization technique to operate in its optimal domain without the harmful side effects of the other, resolving the contradiction between ISI reduction and signal integrity maintenance.

Inventive Principle:
Principle #1Segmentation

4Reliability

If de-emphasis equalization is used to reduce ISI jitter, then ISI jitter is reduced and signal integrity is preserved, but DC power consumption increases

Engineering Contradiction:
ImproveISI jitter reductionVSAvoidDC power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The equalization function is segmented into two distinct parts: TFFE handles the internal data path ISI jitter, while VFFE handles the driver stage ISI jitter. This segmentation allows each equalization technique to operate in its optimal domain without the harmful side effects of the other, resolving the contradiction between ISI reduction and signal integrity maintenance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11082267B1Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter
Publication Date: 2021.08.03 CADENCE DESIGN SYST INC
  • US11082267B1 patent drawing
  • US11082267B1 patent drawing
  • US11082267B1 patent drawing

AI summary

The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.