Shared Redundancy Page Buffer Array for Memory Repair
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Solution Overview
Problem
Conventional memory devices are inefficient in handling a large number of defective cells, leading to discarding of the entire device even when redundant memory arrays from other main memory arrays can potentially replace defective columns, resulting in reduced yield and productivity.
Innovation Solution
A memory device design that includes a shared redundancy memory array and dual redundancy transfer units connected to separate buses, allowing for simultaneous repair operations across first and second main memory arrays, enabling data transfer and access through redundancy page buffers, even when a large number of defective cells exist, thereby increasing repair efficiency and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate redundancy memory arrays are allocated for each main memory array, then each main memory array can be repaired independently, but the overall repair efficiency decreases and yield is reduced when a large number of defective cells exist in one main memory array
Solution Approach 1:
The patent implements a shared redundancy memory array that can serve multiple main memory arrays simultaneously. The redundancy memory array is configured to replace defective columns from either the first or second main memory array, and the page buffer array can switch between different redundancy memory arrays based on which main memory array has defective columns. This multi-functional approach allows one redundancy resource to handle repairs for multiple main arrays, increasing overall yield without compromising repair capability.
2Productivity
If a shared redundancy memory array is used for multiple main memory arrays, then repair efficiency increases and yield improves, but data access stability may be compromised when simultaneous repair operations are performed
Solution Approach 1:
The patent divides the shared redundancy memory array into multiple separate redundancy memory arrays (first redundancy memory array, second redundancy memory array, etc.), with each dedicated to replacing defective columns from specific main memory arrays. The page buffer array is similarly segmented into multiple page buffers, where each page buffer is configured to access specific main and redundancy memory arrays. This segmentation prevents data access conflicts during simultaneous repair operations while maintaining the efficiency benefits of shared redundancy resources.
Solution Approach 2:
The patent introduces a page buffer array as an intermediary between the main memory arrays and redundancy memory arrays. The page buffer array includes multiple page buffers that act as buffers and mediators during data transfer operations. When repair operations are performed, the page buffers temporarily store data and manage the transfer between main and redundancy memory arrays, ensuring data access stability even when multiple repair operations occur simultaneously. This intermediary layer isolates potential conflicts and maintains reliable data access.
Data Source
AI summary
A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.