Variation-Tolerant Word-Line Under-Drive Scheme for RAM
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Solution Overview
Problem
Advanced semiconductor manufacturing processes for RAM lead to variations in process, supply voltage, and temperature, causing degradation in stability, particularly resulting in Read disturb issues due to variations in pass-gate transistor conduction behavior and cell inverter switching points, which affect the Read Static Noise Margin (RSNM) and data integrity during low-voltage operation.
Innovation Solution
A variation-tolerant Word-Line Under-Drive (WLUD) scheme is implemented using first and second tracking transistors that dynamically adjust the word-line enable voltage to track the electronic characteristics of driving transistors and pass-gate transistors, reducing channel conductivity and mitigating Read disturb by maintaining a stable word-line enable voltage against variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If advanced semiconductor manufacturing process (sub-100 nm) is used to scale down RAM layout area and reduce power consumption, then layout area and power consumption are reduced, but process, voltage, and temperature variations cause degradation in RAM stability and increase Read disturb
Solution Approach 1:
The patent implements a dynamic word-line enable voltage adjustment mechanism that adapts to process, voltage, and temperature variations. The system dynamically modifies the word-line enable voltage based on detected variations, allowing the RAM to maintain stability across different operating conditions while using advanced manufacturing processes
Solution Approach 2:
The patent changes the word-line enable voltage parameter to compensate for variations introduced by advanced manufacturing processes. By adjusting this voltage parameter dynamically, the system maintains proper transistor conduction behavior and inverter switching points despite process, voltage, and temperature variations
2Adaptability or versatility
If pass-gate transistor conduction behavior varies due to process, voltage, and temperature variations, then transistor characteristics change, but Read disturb voltage exceeds inverter Trip Voltage causing data flip
Solution Approach 1:
The patent employs a feedback mechanism that detects variations in pass-gate transistor conduction behavior and adjusts the word-line enable voltage accordingly. This feedback loop ensures that the Read disturb voltage remains below the inverter Trip Voltage, preventing erroneous data flipping while adapting to different operating conditions
3Reliability
If word-line enable voltage is lowered to reduce channel conductivity of pass-gate transistors, then Read disturb is reduced, but variation-tolerance requires dynamic adjustment of voltage level
Solution Approach 1:
The patent implements a self-service mechanism where the system automatically detects variations and adjusts the word-line enable voltage without external intervention. The variation-tolerant circuitry monitors transistor characteristics and autonomously modifies the voltage level to maintain optimal operation, reducing Read disturb while adapting to variations
Data Source
AI summary
A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.