Strap Cell Memory Array Segments Bit Lines
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Solution Overview
Problem
Existing memory array designs require external logic circuits and edge cells to connect memory banks, leading to increased circuit size and cost, as well as longer bit lines that result in reduced performance due to increased wire loading and delayed data transmission.
Innovation Solution
The memory array incorporates a strap cell between sub-banks to separate bit lines, allowing them to operate with a shared I/O circuit without external logic circuits or edge cells, reducing bit line length and wire loading, and utilizing separate segments of bit lines and strap cells to improve data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external logic circuits and edge cells are used to connect memory banks, then the memory array can be organized into separate banks, but the circuit area and cost increase
Solution Approach 1:
The patent merges the functions of edge cells and external logic circuits into the strap cell structure. The strap cell is positioned between memory banks and performs both the separation function traditionally requiring external logic and the connection function that would require edge cells, thereby eliminating the need for separate external components and reducing overall circuit area.
Solution Approach 2:
The strap cell is designed as a universal component that performs multiple functions: it acts as a separator between memory banks, provides I/O circuit connectivity, and enables data transmission between banks. This multi-functionality eliminates the need for dedicated edge cells and external logic circuits, reducing device complexity while maintaining memory bank organization flexibility.
2Adaptability or versatility
If external logic circuits and edge cells are used to connect memory banks, then the memory array can be organized into separate banks, but the cost increases
Solution Approach 1:
The patent merges the functions of edge cells and external logic circuits into the strap cell structure. The strap cell is positioned between memory banks and performs both the separation function traditionally requiring external logic and the connection function that would require edge cells, thereby eliminating the need for separate external components and reducing overall circuit area.
Solution Approach 2:
The strap cell is designed as a universal component that performs multiple functions: it acts as a separator between memory banks, provides I/O circuit connectivity, and enables data transmission between banks. This multi-functionality eliminates the need for dedicated edge cells and external logic circuits, reducing device complexity while maintaining memory bank organization flexibility.
3Device complexity
If the circuit area is increased with external logic circuits and edge cells, then memory banks can be connected, but the bit line length increases
Solution Approach 1:
The strap cell serves as an intermediary component positioned between memory banks. It provides a localized connection point that allows bit lines to be routed through the strap cell rather than extending across the entire memory array. This intermediary structure reduces bit line length by creating intermediate connection points, thereby decreasing wire loading and improving signal transmission speed.
4Quantity of substance
If the bit line length is increased, then the memory array can accommodate more cells, but the wire loading increases and performance decreases
Solution Approach 1:
The patent segments the memory array into multiple banks separated by strap cells. This segmentation allows bit lines to be divided into shorter segments that terminate at strap cells rather than extending across the entire array. The segmentation reduces wire loading by limiting the length of continuous bit lines, thereby decreasing capacitive loading and improving signal integrity while still accommodating a large total number of memory cells across multiple banks.
Solution Approach 2:
The strap cell serves as an intermediary component positioned between memory banks. It provides a localized connection point that allows bit lines to be routed through the strap cell rather than extending across the entire memory array. This intermediary structure reduces bit line length by creating intermediate connection points, thereby decreasing wire loading and improving signal transmission speed.
Data Source
AI summary
A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.