Resistive Memory Testing via Constant Current Driver
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Solution Overview
Problem
Conventional testing methods for resistive type memory circuits are ineffective in addressing high error rates and reliability issues, particularly due to their unique physical characteristics, leading to increased testing time and cost as memory size and density increase.
Innovation Solution
A method involving a constant current driver and a common plane voltage (VCP) pad to drive write test currents in parallel through resistive type memory cells, allowing for simultaneous writing and verification of data, and employing design for test (DFT) circuitry for efficient stress testing, retention testing, and functional testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used for resistive type memory circuits, then testing can be performed with standard procedures, but testing effectiveness is poor due to high error rates and reliability issues specific to resistive memories
Solution Approach 1:
The patent modifies testing parameters specifically for resistive memory characteristics. It uses a constant current driver instead of standard voltage-driven approaches, and implements specific voltage levels (VCP pad held at test write voltage level or ground) and pulse widths tailored to resistive memory switching behavior. This resolves the contradiction by adapting parameters to match the unique physical characteristics of resistive memories, improving reliability without requiring completely new complex procedures.
Solution Approach 2:
The patent performs preliminary initialization of memory cells before actual testing. It sets up the VCP pad voltage level and configures the constant current driver in advance, holding them at appropriate levels during the test write pulse width. This preliminary setup ensures that the memory cells are in the correct state for testing, improving reliability while maintaining a systematic approach that doesn't excessive complicate the overall procedure.
2Quantity of substance
If memory size and density increase, then storage capacity improves, but testing time and cost increase proportionally
Solution Approach 1:
The patent merges multiple testing operations into a single unified testing framework. It combines initialization, stress testing, and verification into one integrated process using the constant current driver and VCP pad configuration. This allows testing of larger memory arrays without proportionally increasing testing time, as the method efficiently handles increased density through consolidated operations rather than separate sequential tests.
Solution Approach 2:
The patent maintains continuous testing action throughout the process. The constant current driver continuously drives test currents through the memory cells for the duration of the test write pulse width, and the VCP pad remains held at the appropriate voltage level throughout. This continuous action ensures that even as memory size increases, the testing progresses efficiently without interruptions or redundant setup phases, reducing overall testing time relative to capacity.
3Ease of manufacture
If standard testing approaches are used, then implementation is straightforward, but they fail to address the unique physical characteristics of resistive memories such as STT-MRAM
Solution Approach 1:
The patent applies local quality by tailoring the testing approach specifically to resistive memory characteristics. It uses a constant current driver configured with specific voltage levels (VCP pad at test write voltage level or ground) and pulse width parameters that match the switching behavior of STT-MRAM and other resistive memories. This localized adaptation improves testing accuracy for resistive memory without requiring complete redesign of the entire testing system, maintaining reasonable implementation ease through targeted modifications.
4Productivity
If massive parallel screening is implemented, then test time and cost are reduced, but testing complexity increases
Solution Approach 1:
The patent implements a universal testing framework that can handle multiple memory cells in parallel through the constant current driver. The VCP pad configuration and current driving approach work across entire memory arrays simultaneously, enabling massive parallel screening. The method achieves high productivity by making the testing system multi-functional, capable of testing numerous cells concurrently without requiring separate dedicated circuits for each cell, thus limiting the increase in overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables rapid and reliable screening of memory cells with high error rates, improving the overall reliability and reducing test time and cost by allowing massive parallel testing and initialization of memory circuits.
Implementation Method 1
driving, in parallel, a first write test current to flow in a first direction through the memory cells to write first data to the memory cells
Implementation Method 2
spin transfer torque (STT) magnetoresistive random-access memory (MRAM)
Implementation Method 3
phase change RAM
Data Source
AI summary
Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to a constant current driver, which works in tandem with the VCP pad or external pin to perform massive parallel read or write operations. The inventive concepts include fast test setup and initialization of the memory array. The data can be retention tested or otherwise verified using similar massive parallel testing techniques. Embodiments also include a memory test system including a memory device having DFT circuitry configured to perform massive parallel stress testing, retention testing, functional testing, and test setup and initialization.