3D DRAM Memory Array Layout for Higher Sense Margin
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Solution Overview
Problem
Planar memory cells face density limitations and challenges in scaling due to costly fabrication processes, leading to insufficient sense margin in DRAM architectures, which affects data read reliability.
Innovation Solution
Implement a 3D memory architecture with vertical transistors and capacitors, utilizing metal interconnect layers as shielding structures to increase coupling capacitance and optimize sense margin, and separate fabrication of memory arrays and peripheral circuits on different wafers to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density increases, but fabrication cost increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertical memory cell architecture. The memory cell includes a vertical channel extending from a first surface to a second surface of the substrate, with source and drain regions positioned at opposite ends of the vertical channel. This dimensional change allows continued scaling and density improvement without the same fabrication cost penalties as planar scaling, as the vertical structure utilizes the substrate thickness dimension rather than requiring further lateral miniaturization.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs vertical channel structures that extend through the substrate thickness, utilizing the third dimension (depth) for scaling. This approach shifts the scaling challenge from lateral feature size reduction to controlled epitaxial growth and vertical patterning, which can achieve precise dimensional control through thickness rather than requiring extremely precise lateral lithography and etching at the same feature size scale.
Solution Approach 2:
The patent changes the critical dimensional parameter from lateral feature size to vertical channel length and substrate thickness. By controlling the vertical dimensions through epitaxial growth and substrate preparation rather than lateral lithography, the manufacturing precision requirements are shifted to processes that can achieve controlled thickness and vertical dimensionality, potentially relaxing the most stringent lateral precision requirements.
3Quantity of substance
If 3D memory architecture is implemented, then memory density increases and manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple banks, with each bank containing multiple memory cell arrays. Each memory cell array is further divided into word line groups and bit line groups. This hierarchical segmentation allows the complex 3D structure to be managed in modular units, simplifying the interconnection design and control logic while maintaining high density through the vertical architecture.
4Length of moving object
If feature sizes of memory cells approach lower limit in planar architecture, then scaling is limited, but fabrication process becomes challenging and costly
Solution Approach 1:
The patent implements vertical channel structures that extend from a first surface to a second surface of the substrate, utilizing the thickness dimension for scaling. This allows the effective channel length to be determined by substrate thickness rather than lateral feature size, enabling continued scaling without the same fabrication challenges that limit planar approaches at their minimum feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory area efficiency, reduces capacitor fabrication difficulty, improves DRAM performance and reliability, and allows for further scaling by increasing sense margin and reducing parasitic capacitance.
Implementation Method 1
utilizing metal interconnect layers as shielding structures to increase coupling capacitance and optimize sense margin
Implementation Method 2
allows for further scaling by increasing sense margin and reducing parasitic capacitance
Data Source
AI summary
Semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a memory array structure and a peripheral circuit structure connected with the memory array structure. The memory array structure comprises a transistor layer comprising a plurality of arrays of vertical transistors, a storage layer comprising a plurality of arrays of capacitors coupled with the vertical transistors, a plurality of bit lines coupled with the vertical transistors, and a first interconnection layer comprising a first interconnection structure connected with the plurality of bit lines, and a second interconnection structure disconnected with the plurality of bit lines and connected to a common electrical node. The peripheral circuit structure comprises a second interconnection layer comprising a third interconnection structure connected with the first interconnection structure, and a sense amplifier circuit connected with the third interconnection structure.