3D Stacked DRAM Vertical Cell Layout for Higher Memory Density
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Solution Overview
Problem
Conventional semiconductor device manufacturing is limited by two-dimensional (2D) fabrication techniques, which are approaching physical atomic limitations and require significant substrate surface area for memory cells, hindering the increase in transistor density and efficiency.
Innovation Solution
The implementation of a vertically-stacked 3D capacitor-based memory cell design, where transistors and capacitors are stacked vertically, allowing for a reduced substrate surface area usage and increased circuit density by utilizing a vertical field-effect transistor (VFET) with a cylindrical capacitor, enabling the integration of multiple memory cells in a compact space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D fabrication techniques are used to manufacture memory circuits, then the manufacturing process is relatively simple, but the substrate surface area required is large and transistor density is limited
Solution Approach 1:
The patent transitions from 2D planar fabrication to 3D vertical stacking by forming memory holes extending through multiple layers of materials. Transistors and capacitors are stacked vertically within these holes, utilizing the third dimension (depth) to increase circuit density while reducing the substrate surface area required for memory cell implementation.
2Area of stationary object
If 2D trench-based configuration is used for DRAM cells, then the fabrication process is conventional and well-established, but each DRAM cell occupies significant substrate surface area
Solution Approach 1:
The invention stacks transistors and capacitors vertically within memory holes that extend through multiple layers, transforming the 2D trench-based layout into a 3D vertical structure. This allows multiple memory components to share the same lateral footprint, dramatically reducing the substrate surface area per memory cell.
Solution Approach 2:
The patent nests multiple memory components (transistors and capacitors) within the vertical space of memory holes. The capacitors are positioned above the transistors within the same lateral footprint, creating a nested vertical arrangement that maximizes space utilization and minimizes substrate area consumption.
3Quantity of substance
If vertically-stacked 3D memory cell design is implemented, then circuit density is increased and substrate surface area is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming alternating layers of first and second materials, creating patterns of first and second structures, etching memory holes through specific layers, and forming transistors and capacitors in designated regions. This segmentation makes the complex 3D fabrication process more manageable and systematic.
Solution Approach 2:
The patent performs preliminary actions by pre-forming alternating layers of first and second materials before creating the final memory structure. The memory holes are etched through predetermined layers, and transistors and capacitors are formed in pre-designated first and second regions, respectively. This preliminary structuring simplifies subsequent fabrication steps.
Data Source
AI summary
Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.