3D DRAM Vertical Word Lines Reduce Area and Parasitic Loading
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Solution Overview
Problem
Current DRAM scaling challenges include reducing memory cell area, increasing memory cell density, and achieving higher aspect ratios in the vertical direction, while existing 3D DRAM approaches fail to efficiently consider connections between memory cells and core circuits like sense amplifiers and word line drivers.
Innovation Solution
The proposed 3D DRAM architecture features a vertical word line configuration, with bit lines extending along either the second or third axis, and word lines along the first axis. This design reduces the number of sense amplifiers and word line drivers, optimizing area consumption and minimizing parasitic bit line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D DRAM approaches are used to increase storage capacity, then memory cell density is improved, but area consumption increases due to inefficient connections between memory cells and core circuits
Solution Approach 1:
The patent transitions from conventional planar (2D) arrangements to a three-dimensional (3D) stacked architecture where memory cells are arranged in multiple vertically stacked planes. This vertical stacking enables higher memory cell density while reducing the footprint area by utilizing the third dimension for circuit connections between memory cells and core circuits.
2Quantity of substance
If the number of sense amplifiers and word line drivers is increased to support higher memory cell density, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements shared sense amplifiers and word line drivers that serve multiple memory cell groups across different planes. The sense amplifiers are positioned at the edges of the memory cell array and can sense signals from multiple bit lines, while word line drivers are shared across multiple word lines, thereby reducing the total number of dedicated components while maintaining support for high storage capacity.
3Quantity of substance
If bit lines are arranged in two directions in 3D DRAM, then memory cell density is improved, but placement and routing of sense amplifiers becomes restricted
Solution Approach 1:
The patent divides the memory cell array into multiple blocks or groups, with sense amplifiers positioned at the edges of these blocks. This segmentation allows sense amplifiers to be strategically placed to serve specific regions, simplifying the routing process while maintaining the benefits of bidirectional bit line arrangement for high density.
Data Source
AI summary
The present disclosure relates to a 3D DRAM including a block with a 3D array of memory cells. The block comprises multiple planes stacked along a first axis, each plane comprising a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and the second axis. The block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane. The DRAM further comprising a plurality of bit lines, wherein each bit line extends along the third axis in one of the planes and is connected to one column of memory cells in that plane. The DRAM further comprises a plurality of global bit lines, wherein the global bit lines are connected to the bit lines in each sub-block.