Digital Storage TRIZ Cases

A DQS counter circuit divides data strobe signals to latch write data synchronously with distinct phases.

Segmenting the equalizer function into primary and secondary circuits reduces equalization time by mitigating parasitic RC loading effects.

A magnetic memory cell uses a switch transistor to disconnect the bit line from the magnetic tunnel junction during idle states.

A single column select transistor reduces sense amplifier size and improves array efficiency.

A semiconductor structure uses a pair of magnetic memory structures in complementary states to generate an internal reference signal.

Test and reference detection circuits compare voltage decay to identify leakage currents in nonvolatile memory drive lines.

Synchronizing write port word lines ensures stable PUF-ID generation in SRAM, eliminating the need for power-on/off cycles and reducing chip area.

Alternating even and odd equalizing signals reduce offset and coupling noise in DRAM sense amplifiers, enhancing sensing margin and data reliability.

A semiconductor memory device activates internal address signals before strobe signals to secure sufficient timing margins for data access.

A memory architecture using complementary precharging and overlapping amplification to accelerate data sensing operations.

A resistive switching device programming circuit applies voltage and terminates supply upon reaching a predetermined current threshold.

A control circuit adjusts signal line voltage to float with the bitline during read operations.

A memory device monitors refresh command frequency to enforce compliance standards.

A memory controller reorders program bits to group zero-bits before one-bits, leveraging asymmetrical programming latencies in phase change memory arrays.

Adjusting trigger signal delay based on supply voltage prevents excessive negative bitline pull-down and protects against data corruption.

A segmented pointer comparison circuit maintains high throughput in asynchronous FIFO buffers by dividing large comparator logic into smaller independent stages.

Opposite voltage polarity pulses compensate for thermoelectric asymmetrical heating in small phase change memory elements.

A magnetic random access memory array uses three-terminal nTron circuits to drive wordlines and bitlines for precise cell addressing.

A sense amplifier control module configures an amplification module with a diode structure and current mirror to compensate for offset noise.

Graded metal-nitride electrodes create gradual resistance transitions, resolving abrupt switching limitations in resistive memory for AI processing.

Grouping memory cells by retention time allows dynamic refresh scheduling that reduces redundancy rows and power consumption.

An equalizer circuit shares charge between bit lines to stabilize potentials after write operations in magnetic memory arrays.

A register file circuit uses a header transistor to create a virtual supply node that reduces write contention.

Segmenting write currents into pre-charge and programming phases reduces latency while managing cell damage risks through controlled amplitude timing.

Replacing parallel signal lines with a serial interface reduces manufacturing costs while maintaining high data processing speed for multimedia applications.

Memristive crossbar arrays execute forward propagation and backpropagation using analog signals to accelerate neural network layer computations.

A memory architecture uses a current controller to manage read bit line voltage through controlled current sources.

Vertical word lines in 3D DRAM reduce sense amplifier count and parasitic bit line loading, resolving area consumption trade-offs.

A shared discharge circuit reduces peripheral area in memory devices by serving multiple conductive lines through a single transistor.

Read enable signals traverse I/O pads to introduce calibrated delays for semiconductor sampling.

Strobe signal generation circuit adjusts mode register command timing via variable delay selection.

A static random access memory circuit adjusts retention voltage using a control word derived from detected process variation information.

A memory device pillar structure increases channel width to reduce on-resistance in cell transistors.

A semiconductor integrated circuit adjusts word line activating voltage based on transistor characteristics to optimize memory cell operation.

A clock divider circuit generates odd and even internal clocks to drive a command decoder for precharge operations.

A dual port memory cell couples high voltage to bitlines via a write assist pulse to improve write margin during read-first operations.

A magnetic memory circuit uses a current detector to reduce flow through a series selector while maintaining high voltage.

Separate counters track read operations during queue switches, eliminating pipeline complexity and forced data output restrictions.

In-memory computing circuits compare vector bits to modify pulses, eliminating data transfer latency and energy consumption.

Simulate retention curves to determine programming parameters that stabilize conductive and insulating states against high temperature degradation.

Three-phase word line controllers apply differentiated voltages to adjacent unselected lines, mitigating row hammer disturbances in dense DRAM arrays.

Resonant frequency excitation switches stacked magnetic layers at lower current densities, reducing power consumption while maintaining high storage density.

Segmented memory interfaces transition operating parameters across independent circuit subsets to maintain continuous signal transmission.

A resistive cross-point memory read circuit compares selected cell currents against two distinct reference cells to determine stored data states.

Adjusting array bias voltage via sense lines to compensate for parasitic resistance in SRAM testing circuits.

Multiplexing N test mode signals onto M wires via a pulsed command reduces circuit area and routing complexity in shrinking memory devices.

A method for correcting bit defects in STT-MRAM memory arrays by forcing ambiguous cells to short circuits and mapping them to redundant bits.

A data holding device uses a loop structure and ferroelectric storage driven by distinct power supply voltages.

Activating control unit halts sense amplifier and voltage generating units during data output phases in semiconductor memory devices.