Asynchronous FIFO Circuit Using Segmented Pointer Comparison
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Solution Overview
Problem
Conventional asynchronous FIFO circuits face reduced throughput and operating frequency due to the increased size of comparators with larger data memory depth, leading to metastability issues when the read and write clocks are close in frequency, which affects data transfer rates and synchronization.
Innovation Solution
The proposed asynchronous FIFO circuit eliminates the need for comparators by using a control circuit with a set-clear register bank, multiplexers, and flip-flops to generate memory full and empty signals, allowing asynchronous operation and minimizing metastability, thus maintaining high throughput and frequency stability even with increased data memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the data memory depth is increased to provide larger buffering capacity, then the FIFO circuit can handle greater data rate differences between transmitter and receiver, but the comparator size increases proportionally causing reduced operating frequency and throughput
Solution Approach 1:
The patent segments the pointer comparison function into multiple independent stages. Instead of using a single large comparator to compare all pointer bits simultaneously, the comparison is divided into multiple smaller comparators that operate in sequence or parallel on different portions of the pointers. This segmentation reduces the critical path delay and allows the circuit to maintain high operating frequencies even with deep memory buffers.
Solution Approach 2:
The patent introduces a time dimension to the comparison process by using multi-cycle comparison operations or pipelined comparison stages. Rather than completing the entire pointer comparison in a single clock cycle, the comparison is spread across multiple cycles or stages, effectively trading time for speed in each individual comparison operation. This allows deep memory buffers to be managed without proportionally increasing comparator complexity.
2Quantity of substance
If the data memory depth is increased to provide larger buffering capacity, then the FIFO circuit can handle greater data rate differences, but the comparator size increases causing reduced operating frequency
Solution Approach 1:
The patent segments the pointer comparison function into multiple independent stages. Instead of using a single large comparator to compare all pointer bits simultaneously, the comparison is divided into multiple smaller comparators that operate in sequence or parallel on different portions of the pointers. This segmentation reduces the critical path delay and allows the circuit to maintain high operating frequencies even with deep memory buffers.
Solution Approach 2:
The patent performs preliminary processing of the pointer values before comparison, such as pre-calculation of pointer differences or pre-synchronization of pointers from different clock domains. This preliminary action prepares the data in advance so that the actual comparison operation can be completed quickly, maintaining high operating frequencies regardless of memory depth.
3Reliability
If conventional comparators are used to compare read and write pointers, then the FIFO circuit can track memory occupancy, but the circuit is susceptible to metastability conditions when read and write clocks are close in frequency
Solution Approach 1:
The patent introduces intermediary synchronization stages and metastability resolution circuits between the read and write pointer domains. These intermediaries include multi-stage synchronizers, Gray code converters, and metastability detection circuits that safely bridge the asynchronous clock domains. The intermediary structures provide controlled paths for pointer synchronization that prevent direct metastability propagation to the comparison logic.
Solution Approach 2:
The patent implements preliminary synchronization and validation stages that detect and resolve potential metastability conditions before they can affect the main comparison operation. This cushioning approach uses advance detection of clock domain crossing issues and provides buffered, validated pointer values to the comparison logic, preventing metastability from propagating through the system.
Data Source
AI summary
The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.