Bipolar Switching of Phase Change Memory Elements
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Solution Overview
Problem
Phase change memory devices face difficulties in transitioning from an amorphous high resistance state to a crystalline low resistance state due to 'difficult to set' behavior, especially in small-sized memory elements, caused by asymmetrical heating resulting from thermoelectric effects.
Innovation Solution
Applying reset and set bias arrangements with opposite voltage polarities to overcome asymmetrical heating, where the set bias arrangement includes a voltage pulse with a pulse width of 60 ns or less, effectively compensating for thermoelectric effects and improving heating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the phase change memory element is reduced to achieve higher current densities with smaller absolute current values, then the reset operation becomes more efficient, but the set operation becomes difficult due to asymmetrical heating from thermoelectric effects
Solution Approach 1:
The patent applies opposite polarity voltage pulses for set and reset operations. The reset operation uses a first polarity pulse to melt the phase change material, while the set operation uses a second polarity pulse (opposite to the first) to crystallize it. This inversion of polarity compensates for asymmetrical heating effects that occur in small-sized memory elements, allowing both set and reset operations to function effectively despite the reduced device dimensions.
Solution Approach 2:
The patent changes the voltage polarity parameter between set and reset operations. By switching the polarity of the applied voltage pulse, the direction of current flow reverses, which compensates for thermoelectric heating asymmetry. Additionally, the pulse width parameter is optimized to be 60 ns or less to achieve fast switching while maintaining reliable phase transitions in small-sized elements.
2Speed
If a short voltage pulse of 60 ns or less is applied to achieve fast switching, then the device speed increases for high-speed applications, but the phase transition may be incomplete
Solution Approach 1:
The patent uses pulsed voltage applications with specific timing characteristics. The voltage pulses are applied periodically with widths of 60 ns or less, which provides sufficient energy for complete phase transition while maintaining fast switching speeds. The periodic pulsed action allows the phase change material to undergo complete melting and crystallization cycles within the short pulse duration, ensuring reliable state transitions.
Solution Approach 2:
The patent exploits the phase transition properties of changeable resistive material to achieve fast and reliable switching. By applying voltage pulses that induce complete phase transitions (amorphous to crystalline and vice versa) within 60 ns or less, the device achieves both high speed and reliability. The phase transition mechanism ensures that even short pulses produce complete and stable state changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed of phase change memory devices, making them suitable for high-speed applications like DRAM by ensuring successful transitions between resistance states, overcoming the slow set behavior commonly associated with phase change memory devices.
Implementation Method 1
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Implementation Method 2
current heats the phase change material above a transition temperature to cause transition from the amorphous to the crystalline phase
Implementation Method 3
small bridge-type memory cells which suffer significant thermoelectric effects that cause asymmetrical heating in the body of the phase change material
Data Source
AI summary
Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.