Timing Delay Control Circuit for BTI Compensation

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Solution Overview

Problem

Internal circuits in electronic devices face power gating challenges, particularly with the zig-zag power gating technique leading to bias temperature instability (BTI) issues, which are not present with the header-only technique, affecting timing accuracy in operations like mode register read and read operations.

Innovation Solution

Incorporating a strobe signal generation circuit and data output control circuit to delay and synchronize mode register commands and operation codes, using timing detection and adjustment circuits to generate variable and fixed delay mode register commands, and selection signals to compensate for BTI-induced delays in real-time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If zig-zag power gating technique is used to reduce power consumption, then power efficiency is improved, but bias temperature instability (BTI) phenomenon occurs causing timing accuracy degradation

Engineering Contradiction:
Improvepower consumptionVSAvoidtiming accuracy
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by generating multiple variable delay mode register commands in advance with different delay periods before the actual mode register read operation. These pre-generated commands are stored and selected based on detected timing variations, allowing the system to compensate for BTI-induced delays without real-time calculation overhead during the critical read operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the delay period adaptive rather than fixed. The timing detection circuit continuously monitors timing variations caused by BTI phenomenon and dynamically selects from multiple pre-generated variable delay commands with different delay periods. This dynamic adaptation allows the system to maintain timing accuracy despite power gating-induced threshold voltage shifts.

Inventive Principle:
Principle #15Dynamics

2Reliability

If header-only power gating technique is used to avoid BTI phenomenon, then timing accuracy is maintained, but power gating effectiveness is reduced

Engineering Contradiction:
Improvetiming accuracyVSAvoidpower gating effectiveness
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies segmentation by dividing the single delay control into multiple independent variable delay paths. Each path generates a mode register command with a different delay period, allowing selective use of the most appropriate delay value. This segmentation enables the system to achieve both power gating benefits and timing accuracy by choosing the optimal delay command based on detected timing variations.

Inventive Principle:
Principle #1Segmentation

3Reliability

If variable delay commands are generated to compensate for BTI effects, then timing accuracy is improved, but circuit complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the timing detection circuit to automatically monitor timing variations and select the appropriate variable delay command without external intervention. The system self-adjusts to BTI-induced timing shifts by detecting variations and autonomously selecting from pre-generated delay commands, reducing the need for complex external control mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11308998B2Timing delay control circuits and electronic devices including the timing delay control circuits
Publication Date: 2022.04.19 SK HYNIX INC
  • US11308998B2 patent drawing
  • US11308998B2 patent drawing
  • US11308998B2 patent drawing

AI summary

An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.