SRAM Read Port Bitline Voltage Swing Reduction
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Solution Overview
Problem
SRAM devices face challenges in reducing bitline voltage swings during read operations, especially in sub-threshold voltage conditions, which leads to high power consumption and inefficient memory cell operations.
Innovation Solution
The implementation of a control circuit that adjusts the voltage level on a signal line coupled to a selected bitline, allowing it to float with the bitline voltage, thereby reducing the bitline voltage swing and minimizing power consumption by ensuring that normal memory cells are not fully discharged before a sufficient voltage drop is induced on the worst-case cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bitline voltage is allowed to swing freely during read operations, then the memory cell can be fully discharged for reliable data reading, but the power consumption increases significantly
Solution Approach 1:
The control circuit pre-charges the bitline to a voltage level close to the supply voltage before the read operation begins. This preliminary action ensures that when the read operation starts, the bitline already has sufficient voltage headroom to discharge the memory cell fully without requiring excessive voltage swing during the actual read, thereby reducing power consumption while maintaining reading reliability
Solution Approach 2:
The invention dynamically adjusts the bitline voltage level based on the operational state. During read operations, the control circuit modifies the bitline voltage parameter to float near the supply voltage, preventing excessive discharge. This parameter change optimizes the balance between achieving sufficient voltage drop for reliable reading and minimizing the energy consumed by large voltage swings
2Use of energy by moving object
If the bitline voltage swing is reduced to save power, then power consumption decreases, but the memory cell may not be fully discharged affecting read accuracy
Solution Approach 1:
By pre-charging the bitline to near supply voltage levels before the read operation, the system ensures that even with reduced voltage swing during reading, the bitline maintains sufficient voltage differential to fully discharge the memory cell. This preliminary voltage establishment guarantees read accuracy while allowing the voltage swing to be kept minimal for power savings
Solution Approach 2:
The control circuit monitors the bitline voltage and memory cell discharge state, providing feedback to adjust the bitline voltage dynamically. This feedback mechanism ensures that the bitline voltage is maintained at optimal levels to achieve full cell discharge for accurate reading, while preventing excessive voltage swings that would increase power consumption
Data Source
AI summary
A memory device includes memory cells and a control circuit. Each memory cell includes a first inverter, a second inverter, a first transistor and a second transistor. The first and second inverters are cross-coupled between a first data node and a second data node. The first transistor has a first control terminal coupled to a wordline, a first connection terminal coupled to a bitline, and a second connection terminal. The second transistor has a second control terminal, a third connection terminal and a fourth connection terminal. The second control terminal is coupled to the first data node. The third connection terminal is coupled to the second connection terminal. The control circuit is coupled to the fourth connection terminal, and is configured to, when the bitline is selected, adjust a voltage level at the fourth connection terminal in response to activation of the wordline.