Register File Circuit Header Transistor for Low Voltage Write
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Solution Overview
Problem
Conventional register file circuits face limitations in processor energy efficiency due to the minimum operating voltage required for write operations, which is constrained by contention between NFET and PFET devices, especially at reduced supply voltages, leading to significant energy savings losses.
Innovation Solution
The introduction of a header transistor circuit that includes PFET and NFET transistors to create a virtual supply voltage node, allowing for the clamping of this node below the threshold voltage of the pull-up PFETs, thereby reducing write contention and enabling write operations at lower voltages without degrading completion time, using a programmable pulse generator to optimize pulse width and location for process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the supply voltage is reduced to improve energy efficiency, then energy savings increase, but the minimum operating voltage for write operations increases due to NFET-PFET contention
Solution Approach 1:
A header circuit is introduced as an intermediary component between the write word line and the memory cell. This header circuit includes a header PFET and header NFET that act as mediators to control the write operation. The header circuit eliminates the contention path by providing a dedicated write path that does not involve the main PFET pull-up device, thereby allowing write operations to proceed reliably at lower supply voltages without being constrained by the NFET-PFET contention in the conventional path.
Solution Approach 2:
The write operation path is segmented into two separate paths: a header path for initiating writes and a main path for data retention. The header circuit is separated from the main memory cell circuitry, allowing independent optimization of the write path. This segmentation enables the write operation to occur through a different mechanism that does not suffer from the voltage contention issues affecting the conventional unified path.
2Use of energy by moving object
If the supply voltage is reduced for low-performance applications, then energy efficiency improves, but write operations fail due to increased contention between NFET and PFET devices
Solution Approach 1:
The header circuit serves as an intermediary that facilitates write operations at low voltages. By introducing this intermediate structure with its own transistor pair (header NFET and header PFET), the system creates a write path that is independent of the contentious main path, making write operations easier and more reliable at reduced supply voltages.
Solution Approach 2:
The header circuit introduces dynamic control through additional word line signals (header word line) that independently control the header transistors. This dynamic control mechanism allows the write operation to be initiated and completed through a different timing and control sequence, enabling successful writes at voltages where the static conventional path would fail.
3Adaptability or versatility
If process variation results in slow NFET and fast PFET devices, then NFET-PFET contention is exacerbated, but the minimum operating voltage remains constrained
Solution Approach 1:
The header circuit provides an alternative write path that is less sensitive to NFET-PFET process variations. By using a separate header transistor pair with independent control, the system achieves better adaptability across process corners. The header circuit's independent sizing and control allow it to maintain reliable operation even when the main path transistors exhibit unfavorable process variations.
Solution Approach 2:
The header transistors can be independently sized and configured to optimize performance across different process corners. By changing the parameters (size, threshold voltage) of the header NFET and header PFET separately from the main path transistors, the system achieves better adaptability to process variations while maintaining low minimum operating voltage.
Data Source
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AI summary
A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.