DQS Counter Circuit for Semiconductor Memory Write Operations
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Solution Overview
Problem
In semiconductor memory devices like DRAM, existing technologies face challenges in efficiently managing data strobe signals during write operations, leading to unnecessary signal propagation and potential interference with internal circuits.
Innovation Solution
The implementation of a burst counter within the data control circuit of the semiconductor memory device, which detects the end of write data input and generates appropriate signals to block data strobe signals and reset data latch circuits, thereby preventing unnecessary signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data strobe signal is continuously propagated during write operations, then data input can be maintained, but unnecessary signal propagation occurs causing interference with internal circuits
Solution Approach 1:
The gating circuit is configured to block the data strobe signal in advance after detecting completion of write data input, preventing unnecessary signal propagation to internal circuits before it can cause interference
Solution Approach 2:
The system uses feedback from the completion of write data input to control the gating circuit, which automatically blocks the data strobe signal when writing is complete, ensuring timely prevention of signal interference
2Productivity
If write operations are performed at high frequencies, then productivity is improved, but operation margin is reduced
Solution Approach 1:
The data latch circuit is reset in advance upon detection of write data completion, preparing the circuit for the next write operation and ensuring stable high-frequency operation with adequate timing margin
Data Source
AI summary
An example apparatus includes a dividing circuit configured to divide an original data strobe signal supplied synchronously with a set of write data to generate first to fourth data strobe signals having mutually different phase from one another, a first data latch circuit configured to latch one of the set of write data synchronously with the first data strobe signal, the first data latch circuit being configured to be reset responsive to a first reset signal; a second data latch circuit configured to latch another of the set of write data synchronously with the second data strobe signal, the second data latch circuit being configured to be reset responsive to a second reset signal; and a burst counter circuit configured to activate the first and second reset signals responsive to the third and fourth data strobe signals.