SRAM Array Bias Voltage Compensation for Parasitic Resistance
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Solution Overview
Problem
In large-scale integrated circuits, the variability in parasitic resistance of conductors between the test bias terminal and memory arrays leads to inaccurate power supply voltage application, causing either undertesting or overtesting of SRAM cells, which affects the reliability and yield of memory resources.
Innovation Solution
A method to determine and adjust the power supply voltage for each memory resource by measuring and compensating for individual voltage drops using a test bias terminal and voltage sense lines, allowing real-time control and precise application of the array bias voltage during functional testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power supply voltage is applied to all memory arrays through a common test bias terminal, then the testing process is simplified, but variations in parasitic resistance cause inaccurate voltage application leading to undertesting or overtesting
Solution Approach 1:
The patent divides the memory arrays into multiple groups, with each group connected to a separate test bias terminal. This segmentation allows independent voltage control for each terminal, compensating for parasitic resistance variations in different regions of the integrated circuit without requiring individual control of every single memory array.
Solution Approach 2:
The patent performs preliminary measurement of parasitic resistance values for each test bias terminal before the actual functional testing. These measured values are stored and used to calculate compensation voltages that are applied during testing, ensuring accurate power supply voltage application without adding complexity to the main testing process.
2Reliability
If the power supply voltage is increased to ensure all memory arrays are properly tested, then testing coverage is improved, but memory arrays with lower parasitic resistance are overt tested causing yield loss
Solution Approach 1:
The patent applies different power supply voltages to different test bias terminals based on the specific parasitic resistance characteristics of each terminal's connected memory arrays. This local customization ensures that each group of memory arrays receives the precise voltage needed for proper testing without excessive voltage that would cause false failures and yield loss.
3Measurement precision
If individual power supply voltage control is implemented for each memory array, then voltage accuracy is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent groups multiple memory arrays under common test bias terminals, creating a middle ground between single-terminal and individual-terminal control. This segmentation reduces the number of test bias terminals needed compared to individual control, while still providing regional voltage customization to account for parasitic resistance variations.
Solution Approach 2:
The patent performs voltage compensation calculations in advance based on measured parasitic resistance values, storing these compensation parameters for use during functional testing. This preliminary action eliminates the need for complex real-time voltage adjustment mechanisms, simplifying the overall device structure while maintaining voltage accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate functional testing of SRAM arrays by accounting for variations in parasitic resistance, identifying failing cells without yield loss due to overtesting, and maintaining reliable memory performance.
Implementation Method 1
variations in parasitic resistance of conductors between the test bias terminal and memory arrays leads to inaccurate power supply voltage application
Data Source
AI summary
A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.