STT-MRAM Bit Defect Correction via Short Circuit Forcing
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Solution Overview
Problem
Conventional error correction schemes for STT-MRAM memory devices are inefficient in real-time detection and correction of bit failures, particularly at high defect rates, as they require significant overhead for storing defective bit locations and do not correct errors as data is written, leading to potential system crashes and data corruption.
Innovation Solution
The implementation of a method that adds redundant bits to each codeword in STT-MRAM memory, allowing for real-time detection and correction of defective bits by mapping them to redundant bits during read and write operations, eliminating the need for storing defective bit locations and enabling on-the-fly error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction schemes are used to detect and correct bit failures in STT-MRAM memory, then data integrity can be maintained, but significant overhead is required for storing defective bit locations and the correction process is not performed in real-time
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation to detect defective bits in advance. This allows the system to identify stuck bits, waterfall bits, shunt bits, and low TMR bits before data is written, enabling proactive error correction rather than reactive correction after errors occur.
Solution Approach 2:
The patent introduces an intermediary characterization stage that acts as a mediator between the write operation and data storage. This characterization stage forces defective bits to short circuits and generates correction data that bridges the gap between defective memory cells and reliable data storage, eliminating the need for separate overhead storage structures.
2Reliability
If conventional error correction schemes are used, then bit errors can be detected, but correction is not performed as data is written, leading to potential system crashes and data corruption
Solution Approach 1:
The patent implements continuity of useful action by integrating error correction into the write operation itself. The correction process continues seamlessly as data is written, with defective bits being corrected on-the-fly during the write operation rather than requiring separate correction passes or delaying data access.
Solution Approach 2:
By performing characterization and forcing defective bits to short circuits before the write operation, the system prepares correction data in advance. This preliminary action ensures that when data is written, correction is already in place, eliminating delays between error detection and correction.
3Productivity
If defective bits are not corrected in real-time, then memory operations can proceed without additional processing, but the likelihood of system crashes and data corruption increases
Solution Approach 1:
The patent merges the error correction function with the write operation by forcing defective bits to short circuits during the write process. This combination allows correction to occur simultaneously with data writing, maintaining memory operation speed while improving system stability through real-time error correction.
Solution Approach 2:
The patent converts the harmful effect of defective bits into a beneficial correction mechanism by forcing stuck bits, waterfall bits, shunt bits, and low TMR bits to short circuits. This transformation turns potential error sources into controlled correction opportunities that improve reliability without sacrificing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data integrity by correcting bit defects in real-time, reducing the likelihood of system crashes and data corruption, and extends the memory chip's lifetime by continuously replacing defective bits with redundant ones, even after manufacturing, without incurring large overheads in peripheral circuits.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers
Implementation Method 2
If a spin-polarized current is passed to the magnetic region of a free layer in the magnetic tunnel junction device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer
Implementation Method 3
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing
Data Source
AI summary
A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.