Time Interleaved Sampling Sense Amplifier for DRAM Noise Reduction
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Solution Overview
Problem
Dynamic random-access memory (DRAM) systems face performance deterioration due to offset noise and coupling noise induced by process variations, voltage fluctuations, and temperature changes, which affect the sense amplifier's ability to accurately sense cell voltages.
Innovation Solution
A sense amplifier design that includes a sense amplifying circuit and an equalizing circuit, which induces an offset voltage difference between bit lines, samples voltage changes using drive signals, and adjusts bit line voltages, while an equalizing circuit equalizes bit lines to a pre-charge voltage using alternating even and odd equalizing signals to minimize noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sense amplifier senses voltage differences between bit lines in a DRAM, then data can be read from memory cells, but offset noise and coupling noise reduce the sensing margin and deteriorate performance
Solution Approach 1:
The bit lines are divided into even bit lines and odd bit lines, with separate equalizing circuits (even equalizing circuit and odd equalizing circuit) that operate at different times. This segmentation isolates the sensing operations, preventing coupling noise between adjacent bit lines while maintaining measurement precision through controlled, sequential equalizing operations.
2Productivity
If sense amplifiers operate with adjacent bit lines simultaneously, then throughput is improved, but coupling noise between adjacent bit lines increases
Solution Approach 1:
The equalizing circuits operate in a periodic, alternating manner where the even equalizing circuit operates during even cycles and the odd equalizing circuit operates during odd cycles. This periodic action allows different bit line groups to be equalized and sensed at different time periods, eliminating coupling noise while maintaining high throughput through continuous operation.
3Adaptability or versatility
If offset voltage is induced in sense amplifiers due to PVT variations, then the sense amplifier can be designed with standard components, but offset noise is generated that reduces sensing accuracy
Solution Approach 1:
The equalizing circuits perform preliminary actions before sensing operations by equalizing the bit lines to a predetermined voltage level. This preliminary equalizing action counteracts the offset voltage effects that would otherwise be present due to PVT variations, ensuring that the sensing operation starts from a known, balanced state and improving sensing accuracy while maintaining design flexibility.
Data Source
AI summary
Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.