Memory Architecture Current Controller Read Bit Line Voltage
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Solution Overview
Problem
Current DRAM architectures face limitations in reducing noise sensitivity, power consumption, read time, and increasing memory capacity, with the 1T architecture being susceptible to noise and the 3T architecture requiring complex design changes and high power consumption.
Innovation Solution
A memory architecture with a controlled current source and read switch, using a gain function to control the read bit line voltage, reducing noise sensitivity and power consumption by allowing multi-bit storage without increasing parasitic capacitance and eliminating the need for large logic voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the 1T architecture is used to reduce memory size, then memory area is reduced, but noise sensitivity increases and read reliability deteriorates
Solution Approach 1:
The patent introduces a sense amplifier as an intermediary component between the storage capacitor and the read bit line. The sense amplifier actively detects and amplifies the voltage signal from the storage capacitor, providing a buffered output that is isolated from noise on the bit line. This intermediary structure allows the 1T architecture to maintain small area while improving read reliability through active signal conditioning.
Solution Approach 2:
The patent replaces passive voltage sensing with active current-mode sensing and amplification. Instead of directly sensing small voltage changes on high-capacitance bit lines (passive mechanical-like system), the invention uses active transistors and current mirrors to convert and amplify the signal, substituting the passive sensing mechanism with an active electronic system that provides better noise immunity.
2Reliability
If the 3T architecture is used to improve read reliability, then read reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the functions of the read transistor and the sense amplifier input stage into a integrated structure. The sense amplifier is directly coupled to the storage node through the read transistor, combining the switching function with the amplification function in a unified circuit block. This merging reduces the overall device complexity compared to the separate structures required in 3T architectures while maintaining high read reliability.
3Reliability
If the 3T architecture is used to improve read reliability, then read reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic precharging of the bit lines followed by selective discharge through the sense amplifier during read operations. The bit lines are periodically restored to a reference voltage level, and only during active read cycles is current drawn through the storage capacitor and sense amplifier. This periodic action pattern reduces average power consumption compared to the continuous operation required in 3T architectures while maintaining high read reliability.
Data Source
AI summary
Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold.