Adjustable Trigger Delay for Negative Bitline Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated memory devices, particularly SRAMs, face challenges in writing data into memory cells due to random variations caused by Random Dopant Fluctuation and systematic variations, leading to difficulties in maintaining a stable bitline voltage, especially in subnanometer technologies, which can result in data corruption or bitline damage.
Innovation Solution
A memory device employs a trigger signal with adjustable delay to control the injection of negative charge into a bitline, ensuring it is pulled down to a negative voltage level only when necessary, by varying the delay based on the supply voltage level, using a write assist circuit that operates in both saturated and non-saturated delay regions to prevent excessive voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative bitline scheme is used to enhance write assist, then the signal-to-noise margin is improved, but the bitline voltage may be pulled down to excessively negative levels causing damage
Solution Approach 1:
The trigger signal is generated in advance of the write operation to control the timing of negative charge injection. By preliminarily setting the injection timing based on expected bitline voltage conditions, the system enhances write assist while preventing excessive negative voltage pull-down that would damage the bitline.
Solution Approach 2:
The system monitors bitline voltage conditions and uses this feedback to control when negative charge is injected. The trigger signal timing is adjusted based on the actual voltage state, ensuring that negative charge is only injected when the bitline voltage is sufficiently high, thus preventing excessive negative voltage while maintaining write assist effectiveness.
2Productivity
If negative charge is injected early to assist writing, then the write operation is enhanced, but the bitline voltage drops too early causing excessive negative voltage
Solution Approach 1:
The trigger signal timing is made dynamic rather than fixed. The delay of the trigger signal is adjusted based on the supply voltage level and bitline voltage conditions, allowing the system to optimize write assist timing for different operating conditions while preventing excessive negative voltage pull-down that would compromise reliability.
Solution Approach 2:
The system changes the timing parameter of the trigger signal based on supply voltage level. When supply voltage is high, the trigger delay is increased to prevent early negative charge injection. When supply voltage is low, the trigger delay is decreased to ensure adequate write assist. This parameter adjustment resolves the contradiction between write speed and voltage stability.
3Device complexity
If the trigger signal delay is fixed, then the circuit design is simplified, but the bitline voltage control becomes unreliable across varying supply voltage levels
Solution Approach 1:
The trigger signal delay is made adjustable based on supply voltage level rather than being fixed. This dynamic adjustment mechanism, while adding some complexity to the control logic, ensures reliable bitline voltage control across varying supply voltage conditions by preventing excessive negative voltage pull-down when supply voltage is high.
Solution Approach 2:
The trigger signal delay parameter is changed based on supply voltage level. The system selects different delay values according to the operating conditions, ensuring that negative charge injection timing is optimized for each supply voltage scenario. This parameter adaptation maintains reliability without requiring a completely complex control system.
Data Source
AI summary
Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.