Magnetic Memory Bit Line Equalizer Circuit for Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-power consumption in nonvolatile magnetic memories, particularly during pre-charging or pre-discharging of bit lines, leads to increased energy usage and potential data corruption in half-select states, limiting their application in high-performance processors.
Innovation Solution
The implementation of an equalizer circuit that eliminates potential differences between bit line pairs, allowing charge sharing to set bit lines to a floating state after write operations, reducing power consumption and preventing data corruption in half-select states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-charging or pre-discharging is performed on all bit line pairs to avoid half-select state malfunctions, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent divides the bit line pairs into two groups: selected bit line pairs that require pre-charging/pre-discharging to avoid half-select state, and non-selected bit line pairs that do not require such operations. This segmentation allows the system to perform pre-charging only where necessary, thereby maintaining reliability while reducing overall power consumption.
Solution Approach 2:
The patent applies different operations to different parts of the system: pre-charging is applied locally only to selected bit line pairs that are actively being used, while non-selected bit line pairs are left in their current state. This local quality approach ensures that power-consuming operations are performed only where they are actually needed to prevent malfunctions.
2Use of energy by stationary object
If nonvolatile memory is used as cache memory to reduce standby power, then power consumption is reduced, but operational speed and operational power requirements are not met
Solution Approach 1:
The patent implements periodic pre-charging operations only for selected bit line pairs that are actively being accessed. Instead of continuously pre-charging all bit line pairs, the system performs pre-charging periodically and selectively based on which bit line pairs are currently selected for operation. This periodic and selective approach maintains the nonvolatile memory's low standby power advantage while ensuring that operational bit lines are properly prepared for fast access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption by eliminating unnecessary charging and discharging, stabilizes bit line potentials, and prevents erroneous writing, thereby enhancing the efficiency and reliability of magnetic memory operations.
Implementation Method 1
magnetic memory
Implementation Method 2
allowing charge sharing to set bit lines to a floating state
Data Source
AI summary
A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states.