MRAM Array Architecture Using 3-Terminal nTron for Bit Selection
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Solution Overview
Problem
Current magnetic memory architectures are inefficient, unscalable, and lack the ability to perform bit selection without traditional transistors, resulting in lower memory capacity and larger packaging sizes due to high density and electrical incompatibility.
Innovation Solution
The development of a magnetic random access memory (MRAM) array using three-terminal superconducting devices for efficient read and write operations, incorporating Cryogenic Orthogonal Spin-Transfer (COST) and Cryogenic Spin Hall Effect (CSHE) devices with 3-terminal nTron circuits to enable selective memory cell access and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional transistors are used for bit selection in magnetic memory, then bit select capability is achieved, but energy efficiency deteriorates and device complexity increases
Solution Approach 1:
The patent extracts the bit selection function from traditional transistors by implementing a 1T1R (one transistor one resistor) or 1T1MTJ (one transistor one magnetic tunnel junction) architecture where the transistor is selectively activated only for the targeted memory cell through precise word line and bit line voltage control, eliminating the need for continuous transistor operation and reducing overall energy consumption
Solution Approach 2:
The patent utilizes parameter changes in the magnetic tunnel junction resistance states (high resistance for logic 0, low resistance for logic 1) to enable non-volatile storage and selective reading. By changing the resistance state of the MTJ through spin-polarized current rather than maintaining continuous transistor conduction, energy efficiency is dramatically improved while maintaining full bit select capability
2Quantity of substance
If high density is implemented in magnetic memory arrays, then memory capacity increases, but packaging size increases and electrical compatibility deteriorates
Solution Approach 1:
The patent merges the storage function and address selection function into a unified cross-point array architecture where memory cells are positioned at the intersections of word lines and bit lines. This allows simultaneous addressing and selection of multiple cells through line intersections, dramatically increasing memory capacity per unit area while maintaining electrical compatibility through standardized interconnect schemes
Solution Approach 2:
The patent transitions from linear or planar memory organization to a two-dimensional cross-point array where memory cells are arranged in a grid pattern with word lines extending in one dimension and bit lines in another. This dimensional reorganization enables O(N²) memory capacity scaling without proportional increases in packaging area, as each line intersection provides independent cell access
3Ease of manufacture
If traditional magnetic memory architectures are used, then manufacturing is simplified, but scalability deteriorates and electrical compatibility is poor
Solution Approach 1:
The patent implements a universal memory cell design where the same 1T1R or 1T1MTJ structure serves multiple functions: data storage, bit selection, word selection, and read/write operations. The magnetic tunnel junction acts as both the storage element and the selective access mechanism through its resistance switching behavior, eliminating the need for different structures for different functions and enabling seamless scaling to large arrays
Solution Approach 2:
The patent employs dynamic control of the magnetic tunnel junction state through spin-polarized current injection, where the junction can be switched between high and low resistance states. This dynamic switching capability, controlled by the relative polarity and magnitude of write currents, enables scalable memory operation without requiring static structural modifications, maintaining manufacturing simplicity while achieving high scalability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-density, energy-efficient MRAM arrays capable of handling over 10 GHz clock rates with improved latency, power efficiency, and faster read operations, addressing the limitations of existing magnetic memory architectures by integrating ERSFQ and RQL control logic with 3-terminal nanowire circuits.
Implementation Method 1
The electrical resistance change is a result of the Giant Magnetoresistive effect, which is a quantum mechanical magnetoresistance effect in thin-film structures formed from alternating ferromagnetic and non-magnetic conductive layers
Implementation Method 2
A spin transfer torque (STT) is an effect that modifies the orientation of a magnetic layer in a spin valve device and can be changed using a spin-polarized current
Implementation Method 3
Spin Hall Effect (SHE) is a transport phenomenon for the appearance of spin accumulation on the lateral surfaces of a sample carrying electric current
Data Source
AI summary
A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.