Dual Port Memory Write Assist Circuit
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Solution Overview
Problem
Dual-port SRAM cells in integrated circuits face write margin errors due to reduced timing and voltage margins, leading to operational errors during READ-first operations, especially when transitioning from read to write operations within the same clock cycle.
Innovation Solution
A WRITE assist pulse is generated with a selected delay and duration, coupling a high voltage to the bitlines of the dual-port memory cell after the end-of-read signal, ensuring sufficient voltage is maintained for accurate data writing by replenishing charge on the bitlines and utilizing a trimmable pulse generator to optimize for different operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the current available to the bitlines is increased to drive the SRAM cell harder, then the write margin is improved, but the architecture becomes more complex and latency is introduced
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitlines to a high voltage level before the write operation begins. The write assist pulse is generated in advance of the actual write data transmission, ensuring the bitlines are ready to accept the write operation with sufficient voltage margin. This preliminary preparation eliminates the need for increased current during the write operation itself.
Solution Approach 2:
The patent employs periodic action through the use of write assist pulses that are periodically applied to the bitlines during write operations. These pulses are generated at specific intervals synchronized with the write clock cycle, providing temporary voltage boosting only when needed during the write operation, rather than continuously increasing current.
2Productivity
If the voltage margins are reduced to increase operating speed, then the productivity is improved, but the write operation fails to achieve sufficient voltage level
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage parameter of the bitlines through the write assist pulse. The pulse temporarily increases the voltage on the bitlines during the write operation, effectively changing the voltage parameter at the critical moment when it is needed, without requiring a permanent increase in supply voltage that would compromise speed.
3Productivity
If the timing margins are reduced to increase operating speed, then the productivity is improved, but operational errors occur during READ-first operation
Solution Approach 1:
The patent uses an intermediary approach by introducing the write assist pulse as a mediating element between the read and write operations. The pulse acts as an intermediate voltage boosting mechanism that facilitates the transition from read to write mode, ensuring the write operation can complete successfully even with reduced timing margins.
Data Source
AI summary
A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e.g., Vdd) is coupled to the bitlines (e.g., BL-A, BLc-A) of the first port during the WRITE assist pulse, and a low voltage value (e.g., zero) is written to the memory cell through the second port (e.g., BL-B, BLc-B) during the clock cycle.