Test Mode Signal Multiplexing for Memory Routing Complexity
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Solution Overview
Problem
The complexity of routing test mode signals in memory devices increases with the number of circuits, particularly as semiconductor devices shrink in size, making it difficult to efficiently manage the numerous wires required for signal integrity testing.
Innovation Solution
A test mode signal system that multiplexes multiple test mode signals onto a single wire using a pulsed signal, allowing each signal wire to carry a multiplexed set of signals, and includes a test mode send block for generating and multiplexing signals and a receive block for demultiplexing them, reducing the overall number of wires needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test mode signals are routed separately to all circuits, then signal integrity testing is comprehensive, but the number of wires and routing complexity increases
Solution Approach 1:
The patent combines multiple test mode signals onto a single shared wire by multiplexing them in the time domain. Each test mode signal is transmitted sequentially on the same physical wire, eliminating the need for separate wires for each signal and dramatically reducing routing complexity while maintaining comprehensive testing capability.
Solution Approach 2:
The patent employs periodic time-division multiplexing where test mode signals are transmitted in sequential time slots on a shared wire. The multiplexer switches between different test mode signals periodically, allowing each signal to be transmitted comprehensively while sharing the same physical transmission medium.
2Adaptability or versatility
If the number of circuits within a memory device increases, then device functionality is enhanced, but routing becomes more complex
Solution Approach 1:
The patent merges multiple test mode signal transmission functions into a single shared wire infrastructure. By multiplexing signals in the time domain, the system can support enhanced device functionality with more circuits while using a simplified routing structure that does not scale linearly with the number of circuits.
Solution Approach 2:
The shared wire serves multiple functions by carrying different test mode signals at different time slots. This universal transmission medium can support comprehensive testing of any number of circuits without requiring dedicated routing for each signal, enabling the system to adapt to devices with varying numbers of circuits.
3Area of moving object
If device size is reduced, then integration density is improved, but wire routing becomes more difficult
Solution Approach 1:
The patent merges multiple signal transmission paths into a single shared wire, dramatically reducing the total wire count and routing complexity. This allows device area to be reduced for better integration density without the compounding difficulty of routing numerous separate test mode signal wires through the compact device structure.
Data Source
AI summary
A test mode signal system includes: a test mode block for generating a plurality, N, of test mode signals; a test mode send block, for generating and outputting a pulsed signal according to a command signal, and for multiplexing the N test mode signals in sets according to the pulsed signal and outputting the multiplexed pairs of test mode signals over M signal wires wherein M is less than N, such that each signal wire carries a multiplexed set of the N test mode signals; and a test mode receive block, for receiving the multiplexed sets of N test mode signals and the pulsed signal and demultiplexing each multiplexed set of N test mode signals according to the pulsed signal.