Semiconductor Structure With Pair-Bit MRAM Cells
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Solution Overview
Problem
Current magnetoresistive random access memory (MRAM) technologies, specifically 1T-1MTJ cells, face challenges with small read margins due to the need for a reference signal, which affects data reliability and storage density.
Innovation Solution
The implementation of a semiconductor structure with a pair of magnetic memory structures in complementary states, where one acts as a reference unit and the other as a data unit, eliminating the need for an external reference signal, thereby enhancing read margin, reliability, and memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference signal is provided in 1T-1MTJ MRAM, then data states can be read, but read margin is small
Solution Approach 1:
The patent implements self-service by using one magnetic memory structure within the cell to generate the reference signal internally, eliminating the need for external reference signals. The first magnetic memory structure serves as both a data storage element and a reference signal source, allowing the cell to perform read operations autonomously with improved read margin and reduced system complexity.
2Reliability
If 1T-1MTJ cell structure is used, then manufacturing cost is low and CMOS integration is good, but read margin is small
Solution Approach 1:
The patent merges the reference signal generation function with the data storage function by integrating a first magnetic memory structure that serves dual purposes. This combination allows the cell to achieve improved read margin through internal reference signaling while maintaining compatibility with existing CMOS manufacturing processes and avoiding additional complex external reference signal circuitry.
3Productivity
If bottom electrodes of magnetic memory structures are formed in the same layer, then process steps are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming both bottom electrodes of the first and second magnetic memory structures in the same manufacturing layer during the same process step. This approach consolidates multiple electrode formation operations into a single process step, improving manufacturing efficiency and productivity while the process design ensures that alignment precision requirements are met through coordinated patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high read speed, large read margin, and high reliability by using a pair-bit design in Phase Change Random Access Memory (PCRAM) technology, reducing process steps and costs through simultaneous formation of electrodes in the same layer.
Implementation Method 1
A magnetoresistive random access memory (MRAM) includes a plurality of memory elements with magneto-resistive effects, such as giant magneto resistance (GMR)
Implementation Method 2
A magnetoresistive random access memory (MRAM) includes a plurality of memory elements with magneto-resistive effects, such as giant magneto resistance (GMR) or tunneling magnetoresistance (TMR)
Data Source
AI summary
The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.