Complementary Sensing Memory Architecture for Fast Data Access
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Solution Overview
Problem
In high-density memory systems, the sequential nature of local and global data line sensing limits the ability to decrease access time due to power consumption and timing challenges, particularly in designing for worst-case conditions.
Innovation Solution
A method and memory architecture that precharge local and global data lines to opposite logic states and activate sense amplifiers with programmable delays, allowing for overlapping amplification to achieve fast sensing times, with programmable fuses adjusting timing to compensate for manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If sequential sensing of local and global data lines is used to prevent excessive power consumption, then power consumption is controlled, but access time increases
Solution Approach 1:
The local data lines are precharged to a first logic state and the global data lines are precharged to a second logic state before sensing begins. This preliminary precharging action enables the subsequent overlapping amplification to proceed faster, reducing access time while maintaining power control through the complementary scheme.
Solution Approach 2:
The patent enables overlapping amplification where the local sense amplifier and global sense amplifier operate simultaneously during different phases. The local data line amplification and global data line amplification occur in an overlapping time window, eliminating the sequential waiting period and continuously utilizing sensing resources to reduce access time.
2Stability of the object's composition
If sequential sensing is used to avoid driving to opposite logic states, then device stability is maintained, but sensing speed decreases
Solution Approach 1:
The sensing operation is segmented into distinct phases: a first time window for local data line amplification and a second time window for global data line amplification, with these windows overlapping. This segmentation allows each sense amplifier to operate independently on its designated data lines without interference, maintaining logic state stability while achieving faster overall sensing through parallel phase execution.
Solution Approach 2:
The patent implements dynamic timing control where the local sense amplifier and global sense amplifier are enabled at different times with programmable delays. The timing is adjusted based on manufacturing variations to optimize performance, allowing the system to adaptively balance between stability and speed by dynamically controlling the enable timing of each sense amplifier.
3Reliability
If designers design for worst-case conditions, then reliability is improved, but timing precision deteriorates
Solution Approach 1:
The patent incorporates programmable delay elements that allow the timing parameters of the sense amplifiers to be adjusted. By changing the delay parameters based on actual manufacturing characteristics rather than designing for worst-case conditions, the system achieves optimized timing that is faster while maintaining reliability through programmable adaptation to actual device performance.
Data Source
AI summary
In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.