Shared Discharge Circuit for Memory Peripheral Area Reduction
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Solution Overview
Problem
Existing memory devices face challenges in reducing the area occupied by peripheral circuits, which limits their integration density and efficiency.
Innovation Solution
A memory device design that includes a discharge circuit shared by multiple conductive lines, allowing individual selection and discharge operations, thereby reducing the number of routing lines and the area occupied by the peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a separate discharge circuit is provided for each conductive line, then the discharge operation can be performed independently for each line, but the area occupied by the peripheral circuit increases
Solution Approach 1:
The patent combines multiple discharge circuits into a single shared discharge circuit that serves multiple conductive lines. The discharge transistor is connected to receive control signals and discharge potentials from multiple word lines simultaneously, reducing the total number of discharge circuits from N (one per line) to 1 (shared by all lines), thereby significantly reducing peripheral circuit area.
Solution Approach 2:
The shared discharge circuit is designed to perform discharge operations for multiple different conductive lines through a single transistor. The discharge transistor can be controlled to discharge any of the connected word lines by receiving appropriate control signals, making the circuit universal and multi-functional rather than dedicated to a single line.
2Manufacturing precision
If multiple routing lines are provided for discharge operations, then the discharge control can be precise for each line, but the complexity of the circuit increases
Solution Approach 1:
The patent merges multiple routing lines into a single shared routing structure. Instead of providing separate discharge routing lines for each word line, a single discharge transistor shares the discharge path for multiple lines, reducing routing complexity while maintaining the ability to control discharge for each line through selective activation.
Solution Approach 2:
The shared discharge circuit serves multiple functions by being able to discharge any of the connected word lines. A single circuit structure performs what would otherwise require multiple separate circuits, simplifying the overall device complexity while maintaining precise control over which line is discharged at any given time.
Data Source
AI summary
A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.