Memory Device Pillar Structure for Stable Write Operations
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Solution Overview
Problem
Existing memory devices with resistance change memory elements face challenges in achieving stable write operations due to limited current flow caused by high resistance of cell transistors, which restricts the ability to perform reliable writing to resistance change memory elements.
Innovation Solution
The memory device incorporates a stacked structure with a pillar structure that includes a resistance change portion and a semiconductor portion with a second portion extending from the first portion, increasing the channel width of cell transistors and reducing on-resistance, thereby enhancing the current flow to resistance change memory elements and enabling stable write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel width of cell transistors is increased to reduce on-resistance, then the current flow to resistance change memory elements is enhanced, but the device area increases
Solution Approach 1:
The patent transitions from planar transistor channels to vertically extending pillar structures with channels in the vertical direction. This dimensional change allows the channel length to extend through multiple stacked conductive layers, effectively increasing the channel width equivalent without proportionally increasing the planar device area, thereby reducing on-resistance while maintaining compact footprint.
Solution Approach 2:
The pillar structure nests multiple functional components within a compact vertical arrangement. The semiconductor portion with extended channel is nested within the stacked structure of alternating conductive and insulating layers, allowing the channel to extend through multiple layers. This nesting enables the channel to effectively span a larger volume without proportionally increasing the planar area, thus reducing on-resistance while controlling device area.
2Reliability
If the on-resistance of cell transistors is reduced to enable stable writing, then the write current increases, but the transistor structure becomes more complex
Solution Approach 1:
The transistor structure is segmented into distinct vertical portions: a first semiconductor portion adjacent to the resistance change memory element and a second semiconductor portion extending from the first portion. This segmentation allows each portion to be optimized independently - the first portion for interface with the memory element and the second portion for providing extended channel length - thereby reducing on-resistance through structured complexity rather than random complexity.
Solution Approach 2:
The patent resolves structural complexity by moving the channel extension into the vertical dimension rather than expanding horizontally. The channel extends vertically through stacked conductive and insulating layers, forming a pillar-like structure. This vertical extension achieves the needed channel width equivalent for low on-resistance without requiring complex lateral interconnections or multi-layer planar structures, thus reducing overall device complexity while maintaining reliability.
3Reliability
If the channel width is increased to decrease on-resistance, then the write current to resistance change memory elements increases, but the manufacturing process becomes more difficult
Solution Approach 1:
The manufacturing process benefits from the nested structure where the semiconductor channel is formed within and extends through pre-stacked conductive and insulating layers. This nested arrangement allows sequential formation of layers followed by channel definition, enabling the extended channel structure to be manufactured using standard layered deposition and etching processes rather than requiring complex simultaneous patterning, thus maintaining manufacturing ease while achieving low on-resistance.
Solution Approach 2:
The segmented transistor structure with distinct first and second semiconductor portions aligned with specific conductive layers simplifies manufacturing. Each semiconductor portion can be formed and connected to its corresponding conductive layer in separate manufacturing steps. This segmentation allows for modular fabrication where the channel is built up vertically through defined stages, making the manufacturing process more manageable and scalable compared to forming a single large planar channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the write current to resistance change memory elements, allowing for stable and reliable writing operations by decreasing the on-resistance of cell transistors and increasing the channel width, thus overcoming the limitations of previous memory devices.
Implementation Method 1
a resistance change portion (210) extending in the first direction in the stacked structure
Data Source
AI summary
According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.