Semiconductor Integrated Circuit Word Line Voltage Control
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Solution Overview
Problem
In semiconductor integrated circuits, particularly in SRAM, the miniaturization process leads to increased variations in transistor characteristics and reduced power supply voltage, making it difficult to maintain stable memory cell characteristics, resulting in a trade-off between static noise margin (SNM) and write level, with no established method to determine the appropriate activating voltage for word lines.
Innovation Solution
The semiconductor integrated circuit sets the activating voltage for word lines based on the threshold voltage, saturation current, or drain-source leak current characteristics of p-channel and n-channel transistors, using word line drivers and control circuits to adjust the voltage in response to fabrication variations and environmental changes, including temperature, to optimize both SNM and write level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the activating voltage for word lines is reduced to improve SNM, then the static noise margin is improved, but the write level deteriorates
Solution Approach 1:
The patent applies dynamics by making the word line activating voltage adjustable rather than fixed. The word line driver circuit can dynamically change the activating voltage based on operational requirements, allowing optimization between SNM and write level depending on whether read or write operations are being performed.
Solution Approach 2:
The patent changes the voltage parameter of the word line activating signal. By adjusting the activating voltage to different levels, the circuit can optimize for either SNM (lower voltage) or write level (higher voltage), resolving the trade-off through parameter variation.
2Area of stationary object
If miniaturization processes are used to reduce device area, then the area of semiconductor devices is reduced, but variations in transistor characteristics increase
Solution Approach 1:
The patent measures the threshold voltage of transistors in the memory cell and uses this feedback information to adjust the word line activating voltage. This closed-loop approach compensates for manufacturing variations by adapting the operating parameters based on actual transistor characteristics.
Solution Approach 2:
The patent adjusts the word line activating voltage parameter based on measured transistor threshold voltage variations. By changing this voltage parameter according to actual device characteristics, the circuit maintains stable operation despite miniaturization-induced variations.
3Use of energy by moving object
If power supply voltage is reduced to lower power consumption, then power supply voltage is reduced, but stable characteristics of memory cells become difficult to maintain
Solution Approach 1:
The patent optimizes the word line activating voltage parameter to achieve stable memory cell operation at reduced power supply voltages. By carefully selecting and adjusting this voltage parameter, the circuit maintains adequate SNM and write level even when the overall power supply voltage is lowered.
Data Source
AI summary
A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.