Clock Divider Circuit for DDR SDRAM Precharge Command Segmentation
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Solution Overview
Problem
High-speed electronic devices, such as DDR SDRAMs, face errors in internal command generation due to concurrent input of command and address signals synchronized with the clock, leading to precharge operation errors.
Innovation Solution
The electronic device employs a clock divider circuit to generate out-of-phase internal clocks and a command decoder to produce odd and even precharge commands, each corresponding to multiple clock periods, ensuring synchronized precharge operations across bank groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to operate at high speed, then the operating speed is improved, but command generation errors occur due to concurrent input of command and address signals
Solution Approach 1:
The patent segments the precharge command generation into odd and even precharge commands, each synchronized with alternating clock pulses. This segmentation allows the system to maintain high clock frequencies while preventing command generation errors by processing commands in alternating phases, thus resolving the contradiction between speed and reliability.
2Productivity
If precharge commands are generated in synchronization with the clock, then the operation speed is improved, but precharge command pulses may merge causing operation errors
Solution Approach 1:
The patent implements periodic action by generating odd precharge commands in synchronization with odd clock pulses and even precharge commands with even clock pulses. This periodic alternation ensures that command pulses are distributed evenly over time, preventing merging while maintaining high operation speed.
Solution Approach 2:
The patent extracts the precharge command generation from the single clock synchronization stream and divides it into two separate synchronization streams (odd and even). This extraction prevents the merging of command pulses by creating temporal separation, thus maintaining both speed and reliability.
3Device complexity
If a single internal clock is used for all operations, then the device complexity is reduced, but command and address signal conflicts occur during precharge operations
Solution Approach 1:
The patent segments the single internal clock into two separate internal clocks (first internal clock for odd pulses, second internal clock for even pulses). This segmentation eliminates command and address signal conflicts during precharge operations by providing separate timing references, while the overall complexity remains manageable through systematic clock division.
Data Source
AI summary
An electronic device may include: a clock divider circuit configured to generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command/address signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock.