Resistive Memory Write Circuit Segmented Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently controlling memory cells to achieve lower resistance states during write operations, particularly in minimizing pre-write latency and write latency times, which affects the reliability and speed of data storage.
Innovation Solution
The implementation of a semiconductor memory device with a write circuit that generates distinct write currents at different times based on pre-write latency and write latency, utilizing a first write current for initializing a crystal seed and a second write current for accelerating the set program operation, thereby reducing the time required for achieving a lower resistance state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single write current is used for memory cell programming, then the write operation is simpler, but the time required to achieve the desired resistance state (write latency) is longer
Solution Approach 1:
The write current is segmented into two distinct currents: a first write current (Iw1) applied during a first time period, and a second write current (Iw2) applied during a second time period. This segmentation allows each current to be optimized for different stages of the programming process, reducing overall write latency while maintaining manageable circuit complexity through structured control blocks.
Solution Approach 2:
The first write current (Iw1) is applied in advance during a pre-charge period before the main programming operation. This preliminary action prepares the memory cell by establishing initial conditions that facilitate faster subsequent programming with the second write current, thereby reducing the total write latency without significantly increasing circuit complexity.
2Speed
If the write current amplitude is increased to reduce write latency, then the programming speed improves, but the risk of damaging the memory cell or causing excessive disturbance to non-selected cells increases
Solution Approach 1:
The write operation is divided into two stages with different current amplitudes: the first write current (Iw1) uses a lower amplitude during the pre-charge period to avoid damage, while the second write current (Iw2) uses a higher amplitude for faster programming. This segmentation allows the system to achieve high programming speed without excessive damage risk by applying high current only when necessary and for a limited duration.
Solution Approach 2:
The write circuit employs periodic action by applying currents in distinct time periods: a first period for pre-charging with lower current, followed by a second period for main programming with higher current. This periodic structure enables the system to balance programming speed and cell safety by controlling when high-amplitude current is applied, thereby reducing overall damage risk while maintaining fast programming.
3Loss of time
If pre-write latency is reduced to improve overall write performance, then the time to start write operations decreases, but the complexity of write control increases
Solution Approach 1:
The write control block performs preliminary actions by generating the first write current (Iw1) and applying it to selected memory cells during a pre-charge period before the main write operation. This preliminary current application prepares the cells in advance, reducing the effective pre-write latency for the subsequent main programming operation. The control complexity is managed through structured timing signals that coordinate the sequential application of different currents.
Solution Approach 2:
The write control block dynamically adjusts the write current characteristics by switching between different current amplitudes and time periods based on the programming stage. This dynamic control enables reduced pre-write latency through adaptive current management, where the system automatically transitions from the first write current (Iw1) during pre-charge to the second write current (Iw2) during main programming, balancing speed improvement with controlled complexity.
Data Source
AI summary
An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.