3D Semiconductor Electrode Segmentation for Dense Reliable Memory
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of fine pattern forming technology, making it impractical to increase density, while three-dimensional semiconductor devices offer a solution but require innovative structural designs to enhance reliability and density.
Innovation Solution
A semiconductor device with a substrate featuring a cell array region and connection region, vertically stacked electrodes and pads, central and peripheral vertical structures, and a separation insulating pattern that divides electrodes into multiple portions, enhancing structural integrity and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern forming technology to increase integration, then integration density is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple electrode layers (first electrode layer, second electrode layer, third electrode layer) are stacked vertically with间隔 insulating layers between them, enabling higher integration density without requiring finer lateral patterning. This vertical stacking approach directly addresses the contradiction by moving the integration increase from the lateral dimension to the vertical dimension.
2Quantity of substance
If three-dimensional semiconductor devices use complex structural designs to enhance density, then integration density is improved, but device reliability may deteriorate
Solution Approach 1:
The patent divides the three-dimensional structure into multiple discrete electrode layers (first, second, and third electrode layers) separated by间隔 insulating layers. Each electrode layer can be independently formed and controlled, allowing for better stress management and reduced mutual interference between adjacent electrodes. This segmentation approach maintains device reliability while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent introduces间隔 insulating layers as intermediary structures between adjacent electrode layers. These insulating layers provide electrical isolation and mechanical support, preventing direct contact and potential short circuits between the first, second, and third electrode layers. The intermediary insulating layers enable the vertical stacking structure to maintain both high density and reliable operation.
Data Source
AI summary
A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.