Read-Only Memories TRIZ Cases

Simultaneous bit-line and source-line channel precharge initializes 3D NAND strings before programming to curb disturb and hot carrier injection.

A charge integrator measures bit-line charge at stable voltage, avoiding parasitic-capacitor attenuation and improving read accuracy.

Rectifier-based anti-fuse memory blocks unintended charge injection and disturbance while sharing contacts to shrink cell area.

Adaptive pulse polarity and count programming handles cell threshold variation to widen read windows and cut multi-level memory errors.

A resistor-based current detector flags leaking flash memory word lines during programming, helping isolate bad blocks before data loss.

Multi-level pass voltages on neighboring word lines isolate a selected 3D NAND cell, improving programming accuracy and data reliability.

Split gate conductor layers suppress word-line coupling noise in capacitorless DRAM while enabling concurrent page read and refresh.

Stored write-time temperature data guides read voltage selection in non-volatile memory, cutting read errors without slow voltage tracking.

A virtual cell mode uses a current mirror and page buffer to verify nonvolatile memory current sensing without the memory cell array.

A two-stage read pass voltage discharge lowers peak Icc in 3D memory reads while preserving fast sensing and uniform current profiles.

Fixed-value readback lets a memory controller verify bit detection and peripheral circuits, improving functional safety in onboard systems.

Separated upper electrodes and vertical stacks raise memory density while preserving reliability without finer 2D patterning.

Dual read retry tables adjust voltages for open and closed blocks, improving NAND read accuracy despite word line voltage offsets.

Adaptive program verify settings raise target voltage in partially functional blocks to offset defective deck shifts and lower memory errors.

Bit-line GIDL hole generation enables selective erase of one 3D NAND block on a shared string while protecting data in adjacent blocks.

Adjusts erase verification voltage from pulse-count feedback to limit program interference early and cycling degradation later.

Dividing a 3D NAND block into subblocks lets control logic adapt erase, read, and program strategy to each subblock state with less wear.

Stair-step structures and segmented vertical access lines improve electrical coupling in stacked memory arrays while easing manufacturing complexity.

Buried source and p-doped injection wells enable dense 3D NAND vertical channels while preserving alignment and memory functionality.

A preset-voltage read checks fail bit count after first programming, enabling targeted second programming with less error correction overhead.

Sequentially shifting memory cells to higher Vt levels avoids intervening erase steps, reducing PE stress, latency, and wear.

Segmented stacked layers and a bended vertical gate stack ease high-aspect-ratio etching while lowering channel resistance for denser memory.

Threshold-tail cells are bit-level erased or programmed in place to cut read errors and recover non-volatile memory data.

Radiation exposure sensing triggers refresh, read-voltage adjustment, and fault repair to protect 3D flash data with less shielding.

Adaptive sub-block programming voltage based on erase count limits unselected sub-block disturb while reducing relocation and write amplification.

A lower isolation structure and matched staircase support members prevent layer and word-line collapse in dense 3D memory fabrication.

Independent source segments replace segregated select gates to shrink memory blocks and improve threshold voltage consistency during sub-block access.

Power-gate and cascode-gate transistors cut leakage and cell area in fuse memory, improving read margin and reliability.

Different threshold voltages on shared bottom select gates cut parasitic RC delay and shorten programming time in dense 3D NAND.

Code table mapping splits target data bits across memory cells to cut read counts and improve multi-bit storage efficiency.

Different program voltage steps for separate memory regions improve threshold alignment, read window margins, and data reliability.

A code-table scheme splits target bits across memory cells to cut read overhead and improve multi-bit storage integrity.

Multiple NAND memory decks are selectively connected in parallel to improve current flow and array operation using threshold-programmed select gates.

A pre-read between program passes detects charge-loss voltage shifts and updates the next program voltage to reduce NAND flash bit errors.

Adaptive threshold-voltage scans track select gate degradation by P/E cycles, reducing host timeouts while preserving memory block reliability.

Deck-specific seeding voltages and deck separation reduce program disturb while preserving programming speed in multi-deck memory arrays.

A ferroelectric layer around the channel and a back gate inside it improve 3D flash cell reliability while supporting faster program, erase, and read.

Dummy bit lines placed beside the common source line shield read bit lines from noise, improving sensing accuracy and memory reliability.

A weak erase pulse uses GIDL to discharge 3D NAND pillars, easing boosting stress and improving data retention without added latency.

Adjacent word line data corrects threshold voltage shifts before soft decoding, improving multi-level memory read accuracy under cell interference.

Multi-level verify and selected bit line voltages narrow memory-cell threshold distributions while shortening non-volatile programming time.

Channel precharge from the source or drain side cuts program disturb in independently programmed memory sub-blocks while keeping word-line programming efficient.

A single SONOS TFET merges storage and comparison to shrink TCAM cell area and cut power for database search and in-memory computing.

Unequal bit-line wiring lengths create RC load offsets; this case shows how compensation loads equalize sensing paths for accurate memory reads.

A recessed vertical memory cell uses impact ionization and GIDL to curb leakage while preserving operating margin and data retention.

A nonvolatile memory device sets individual read voltage levels for each error correction code unit to optimize data detection accuracy.

A unit-distance code maps read voltages to memory pages, minimizing average voltage drift ranges to decrease error rate discrepancy between pages.

A semiconductor device uses a voltage control circuit to supply distinct voltage levels to decoders, enabling stable signal handling across memory blocks.

Grouping word lines by program time minimizes performance degradation caused by timing variations during semiconductor memory programming.

Dynamic programming pulses adjust voltages based on adjacent cell verification status to prevent program disturb without increasing overall programming time.

Adjusting conductance mapping values in crossbar array circuits to reduce current consumption.

Decoding method determines optimized read voltages from Gray code count differences without verified data, reducing computational resources and storage needs.

Segmented erase counter fields store selection codes and address information to determine physical memory addresses.

Regulation circuitry compares bit line current against a reference level to set clamp transistor control gates for precise memory sensing.

A shielding layer with a conduction region sits between peripheral devices and memory strings in 3D memory architectures.

A reset controller initializes data storage during the evaluation period to accelerate memory read operations.

A semiconductor integrated circuit selects bit line voltages based on program data to enable simultaneous strong and weak programming.

Trial programming calibrates initial pulse magnitude based on threshold voltage ranges to prevent over-programming in aging devices.

Monitoring circuits test transmit lines during power-up to detect faults, preventing degradation from compromising memory device reliability.

A memory device uses a security register with a register-protection bit to lock the status register write-protect state.

Host clock signal detects supply voltage level to configure core regulator mode, eliminating configuration pins and substrate designs.

Controller prevents subsequent writes to OTP locations by verifying cell states with distinct low-voltage reads, eliminating dedicated locking circuitry.

Combining adjacent memory cells into a single program and erase entity enables quad-bit storage, resolving the sector erasure bottleneck.

A semiconductor latch circuit stores setup information for multiple operation modes using a universal storage structure.

A sensing node pre-charges through a voltage-supply node to resolve latch reset delays that increase recovery time and degrade sensing accuracy.

Identical-footprint write assistance cells pre-charge bit lines to mitigate parasitic effects, ensuring reliable writing despite reduced wiring dimensions.

A memory system uses resistance states in a second storage block to map logical addresses directly to physical word lines.

A dummy cell absorbs capacitive coupling to maintain flag cell threshold voltage levels.

Reorienting program-erase and select gate lines vertically within a three-gate flash memory cell array enables independent single-bit addressing.

Binary repair cells store redundancy signals to substitute faulty memory units, eliminating complex decoding logic and reducing die area.

A multi-rail sense circuit uses pre-charge transistors to equalize sense nodes at VDD2 before sensing begins.

A voltage generation circuit uses a shared detection unit to monitor program and erase voltages sequentially.

Stepped write pulses suppress threshold voltage distribution spread in degraded insulating films, ensuring accurate data retention.

A nonvolatile memory device applies distinct bit line voltages to selected and unselected cell strings during partial read operations.

Segmenting page buffer groups into staggered activation periods reduces peak current and voltage drops during sense node precharge operations.

Merging separate control circuits into one unit reduces manufacturing costs and IC volume while protecting the OTP area from unauthorized erasure.

A memory controller adjusts read voltages using a temperature table to optimize data retrieval accuracy.

A trimming circuit adjusts a voltage divider ratio to control regulator output.

Vertical pillar structure in NOR flash memory cells enables high integration density without scaling planar dimensions.

A sensing circuit detects resistive memory states by pulling voltage based on resistance relative to a threshold.

A nonvolatile memory cell uses two data storage layers to store data via distinct program voltages.

Time multiplexing controls temperature-dependent and independent voltage components, reducing device complexity and power consumption.

A semiconductor controller adjusts word line voltages to estimate optimal reading levels for multi-bit data retrieval.

Multi-pass programming method adjusts pass voltages on adjacent word lines to compensate for capacitive coupling during flash memory verification.

Dynamic voltage adjustment compensates for threshold shifts, preventing data corruption during flash memory read operations.

A 2-transistor vertical memory cell uses shield structures to reduce capacitive coupling between adjacent charge storage nodes.

Reordering data latches into sequential binary code reduces dumping operations during programming, cutting verification time while maintaining reliability.

Precompensates target threshold voltage using neighbor cell coupling ratios to minimize programming errors in flash memory arrays.

A nonvolatile memory device performs a second program operation on adjacent open wordlines to convert no-coupled states into coupled ones.

Segmenting erase verification by targeting only failed word lines reduces operation time while maintaining high reliability for nonvolatile memory devices.

A voltage regulator adjusts the differential between access lines and control gates in string drivers to optimize programming pulses.

A memory page buffer circuit adjusts pre-charge operations based on detected temperature to maintain stable data reading performance.

A hybrid latch and eFuse scheme identifies redundant memory elements to reroute operations.

Self-aligned contact formation in a 3D memory device eliminates staircase etching defects while boosting throughput and reliability.