Memory Block Precharge Direction for Program Disturb Control
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Solution Overview
Problem
Existing memory devices face inefficiencies in programming word lines due to program disturb issues, particularly when word lines in different sub-blocks are programmed in opposite directions, leading to performance inconsistencies and potential errors.
Innovation Solution
A method and apparatus for programming memory devices that divide memory blocks into sub-blocks, allowing independent programming and erasing, with word lines programmed sequentially from the drain side to the source side, incorporating pre-charging processes based on sub-block location and programming conditions to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines in upper sub-block are programmed from source side towards drain side and word lines in lower sub-block are programmed from drain side towards source side to minimize program disturb, then program disturb is reduced, but programming efficiency and consistency deteriorate due to opposite programming directions
Solution Approach 1:
The memory block is divided into multiple sub-blocks (upper sub-block and lower sub-block) that can be programmed independently. This segmentation allows different programming strategies to be applied to different sub-blocks, optimizing both program disturb reduction and programming efficiency for each segment based on its specific conditions
Solution Approach 2:
The programming direction is made dynamic rather than fixed. The control circuitry determines the programming direction for each sub-block based on real-time conditions such as which sub-block is currently being programmed and the programming status of other sub-blocks. This dynamic adaptation resolves the contradiction by allowing opposite directions when necessary for program disturb reduction while maintaining consistent direction when it improves efficiency
2Reliability
If word lines are programmed sequentially in opposite directions in different sub-blocks to reduce program disturb, then program disturb is minimized, but programming time and operational complexity increase
Solution Approach 1:
The control circuitry performs preliminary determination of the programming direction for each sub-block before actual programming begins. By analyzing the current state of memory blocks and predicting the optimal programming sequence, the system prepares the programming schedule in advance, reducing actual programming time while maintaining program disturb reduction benefits
Solution Approach 2:
The programming operation maintains continuity by allowing different sub-blocks to be programmed simultaneously or in optimized sequences. Rather than completing one sub-block entirely before starting another, the system can overlap programming operations across sub-blocks with different directions, reducing total programming time while maintaining reliability
Data Source
AI summary
The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.