3D Memory Device Self-Aligned Contact Formation
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Solution Overview
Problem
Conventional 3D memory device fabrication techniques face challenges such as high costs and decreased productive throughput due to the complexity of staircase formation, which includes defects from inaccuracy in process steps like over-etching, under-etching, and misalignment of contact holes, limiting memory density and reliability.
Innovation Solution
A method for forming a 3D memory device involving an alternating dielectric stack with sacrificial layers, where contact holes of varying depths are formed using a hard mask and photoresist layer, followed by sacrificial-filling and replacement with conductive layers to create gate lines and contacts, eliminating the need for a conventional staircase structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional staircase formation with dedicated reticles and lithography/etching processes is used, then the 3D memory structure can be formed, but the cost significantly increases and productive throughput decreases
Solution Approach 1:
The patent merges the formation of contact holes with the formation of gate lines by using the same lithography and etching processes. The contact holes are formed at different depths simultaneously with the gate lines, eliminating the need for separate staircase formation processes and dedicated reticles, thereby significantly improving productive throughput
Solution Approach 2:
The patent uses sacrificial layers deposited between dielectric layers as a preliminary structure that enables subsequent self-aligned contact hole formation. These sacrificial layers are removed after contact hole formation to create the final 3D memory structure, allowing complex contacts to be formed through simpler, more efficient processes
2Reliability
If conventional staircase formation with masking-etching processes is used, then contacts can be formed at increased depth, but defects occur due to process inaccuracy including over-etching, under-etching, and misalignment
Solution Approach 1:
The patent employs self-aligned contact hole formation where the contact holes are automatically positioned and formed at the correct depths using the sacrificial layer structure as a guide. The process uses the same lithography and etching steps that form the gate lines, ensuring inherent alignment and eliminating misalignment defects
Solution Approach 2:
The sacrificial layers act as an intermediary structure that enables precise contact hole formation at different depths. These sacrificial layers are removed after contact hole formation to create the final 3D memory structure, allowing complex contacts to be formed through simpler, more precise processes without the defects of conventional methods
3Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density can be increased, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar memory architecture to three-dimensional vertical stacking, forming memory cells in the vertical dimension rather than scaling laterally. This allows memory density to be increased without further reducing feature sizes, avoiding the manufacturing challenges and costs associated with scaling planar cells to smaller dimensions
Data Source
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AI summary
A method for forming 3D memory device includes forming an alternating dielectric stack in a contact region on a substrate, forming a plurality of contact holes with various depths vertically extending in the alternating dielectric stack, forming a sacrificial-filling layer to fill the contact holes, forming a plurality of dummy channel holes penetrating the alternating dielectric stack in the contact region, filling the dummy channel holes with a dielectric material to form supporters, and replacing the sacrificial layers of the alternating dielectric stack and the sacrificial-filling layer with conductive layers so as to form a plurality of gate lines and contacts.