3D NAND Vertical Channels With Charge Injection Wells
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Solution Overview
Problem
Existing three-dimensional memory structures face challenges in efficiently integrating vertical NAND strings and other three-dimensional devices, particularly in forming monolithic memory arrays with high density and functional integrity.
Innovation Solution
The method involves forming a substrate with a buried source semiconductor layer and p-doped semiconductor material portions, followed by an alternating stack of insulating and sacrificial material layers, and creating memory openings with charge storage and tunneling dielectric layers to construct vertical NAND strings, utilizing conformal deposition and etching techniques to achieve precise structural formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND strings are integrated with other three-dimensional devices in existing structures, then device density is improved, but manufacturing complexity and functional integrity deteriorate
Solution Approach 1:
The patent divides the three-dimensional memory structure into distinct functional segments: charge carrier injection wells, vertical channels, tunneling dielectric layers, and charge storage layers. Each segment is formed through separate, optimized processing steps that can be independently controlled, reducing manufacturing complexity while achieving high device density through vertical stacking
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by forming vertical channels extending through alternating insulating and sacrificial layers. This dimensional change enables significantly higher device density by utilizing the vertical dimension for stacking multiple memory cells, while the modular layer-by-layer fabrication approach maintains manufacturing feasibility
2Reliability
If vertical channels are formed with charge storage layers, then memory functionality is improved, but structural precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by first forming the alternating stack of insulating and sacrificial material layers before creating the vertical channels. The sacrificial layers are pre-positioned to define the exact locations where vertical channels will later be formed, ensuring precise structural alignment. Charge carrier injection wells are also formed in advance to prepare the structure for subsequent channel formation, reducing precision requirements during critical steps
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures that temporarily occupy the space where vertical channels will eventually form. These sacrificial layers act as placeholders and guides during fabrication, enabling precise channel formation through selective removal. The intermediary sacrificial structure simplifies the manufacturing process by providing a template that ensures accurate positioning without requiring direct high-precision formation of the final channel structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density, monolithic three-dimensional NAND strings with improved integration and functionality, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
improves the efficiency and reliability of charge carrier injection
Implementation Method 2
p-doped semiconductor material portions embedded within the n-doped buried source layer
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n- doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.