3D NAND Bottom Select Gate Control for Faster Programming
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Solution Overview
Problem
The reduction in peripheral circuit area and limited driving capability of array voltage in complementary metal oxide semiconductor circuits leads to increased programming time in high-density memory cells, affecting performance and reliability.
Innovation Solution
Implementing a memory device with a bottom select gate layer that includes bottom select gates connected to the same select line, and programming these gates to different threshold voltages to achieve selective turn-on and turn-off, reducing the parasitic RC effect without physical separation, thus improving programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased in 3D NAND, then storage capacity is improved, but programming time increases due to reduced peripheral circuit area and limited driving capability
Solution Approach 1:
The bottom select gate layer is divided into multiple independent bottom select gate lines (first bottom select gate line, second bottom select gate line, third bottom select gate line), each capable of being independently controlled. This segmentation allows selective activation of different memory string groups, reducing the parasitic RC effect by isolating active memory strings from inactive ones, thereby decreasing programming time while maintaining high memory cell density
Solution Approach 2:
The patent implements dynamic control of bottom select gates by assigning different threshold voltages to different bottom select gate lines and selectively applying voltages during programming operations. This dynamic switching capability enables optimal control of memory string activation, reducing parasitic effects and improving programming speed in high-density memory structures
2Device complexity
If bottom select gates in different memory strings are connected to the same select line, then device complexity is reduced, but parasitic RC effect increases affecting programming performance
Solution Approach 1:
The bottom select gate layer is segmented into multiple independent bottom select gate lines instead of using a single shared line. Each bottom select gate line can independently control its associated memory strings, which reduces the parasitic RC effect by limiting the capacitive loading on each select line while maintaining relatively simple device structure
Solution Approach 2:
Different bottom select gate lines are assigned different threshold voltages and control characteristics tailored to their specific memory string groups. This local optimization allows each select line to be optimized for its specific load, reducing parasitic effects locally while maintaining overall system simplicity
Data Source
AI summary
A memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.