Memory System with Resistance-Based Address Mapping
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Solution Overview
Problem
Conventional memory systems experience delays in reading or writing data due to the time-consuming logical-physical address conversion process, which becomes more significant as storage capacity increases, as the controller needs to read and process a large logical-physical address conversion table.
Innovation Solution
The memory system shifts the logical-physical conversion function from the controller to the second storage, where word lines of the second storage are directly connected to the first storage, allowing the second storage to perform the conversion by setting resistance states of its memory cells based on logical addresses, thereby bypassing the need for the controller to read and process the conversion table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the controller performs logical-physical address conversion by reading the conversion table, then the address conversion can be completed, but the processing time increases significantly
Solution Approach 1:
The patent pre-loads the logical-physical address conversion table into the second memory block (buffer memory) before data access operations. This preliminary action allows the conversion table to be readily available in fast memory, eliminating the time penalty of reading from slower flash memory during actual data operations, thus resolving the time loss contradiction
Solution Approach 2:
The patent introduces a buffer memory (second memory block) as an intermediary between the controller and the flash memory. This buffer memory stores the address conversion table and acts as a mediator that speeds up the address conversion process, preventing the bottleneck that would otherwise slow down data processing productivity
2Quantity of substance
If the storage capacity is increased, then more data can be stored, but the address conversion table size increases causing longer processing time
Solution Approach 1:
The patent segments the memory system into two distinct blocks: a first memory block for data storage and a second memory block for storing the address conversion table. This segmentation allows the conversion table to be separated from the main data storage, enabling it to be loaded into faster memory without proportionally increasing the time loss, even as storage capacity expands
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the processing speed for reading and writing data by eliminating the need for the controller to perform the address conversion, reducing processing time and enhancing overall system efficiency.
Implementation Method 1
The resistance states of the plurality of second memory cells included in the second storage are set to at least a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between logical addresses and word lines of the first storage
Data Source
AI summary
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.