3D NAND Subblock Operation Control for Small-Capacity Blocks
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Solution Overview
Problem
The increasing number of layers in 3D NAND memory devices poses a challenge in accommodating memory cell array blocks with small capacities without significant firmware updates.
Innovation Solution
A memory device with a memory cell array block divided into two subblocks, each with distinct programming and erasing strategies based on the state of the other subblock, using a control logic to manage operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in the stacked structure of a 3D NAND memory is increased to increase capacity, then the storage capacity increases, but the ability to accommodate small capacity memory cell array blocks deteriorates
Solution Approach 1:
The memory cell array block is divided into multiple subblocks (first subblock and second subblock), each capable of independent operation. This segmentation allows the system to selectively activate only the required number of subblocks based on capacity needs, enabling small capacity configurations even in high-layer-count devices designed for large capacity.
2Adaptability or versatility
If the memory cell array block is divided into multiple subblocks with independent operations, then the adaptability for different capacities improves, but the device complexity increases
Solution Approach 1:
The control logic is designed with multi-functionality to handle both block mode and subblock mode operations. The same control logic structure manages erasing, reading, and programming operations across different configurations (full block or individual subblocks), reducing the need for separate control paths and minimizing firmware complexity despite the divided architecture.
Data Source
AI summary
A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each memory cell array subblock comprising layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.