Non-Volatile Memory Error Updating for Threshold Tail Correction

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Solution Overview

Problem

Non-volatile memory systems face challenges in reliably reading data due to high error rates, particularly from memory cells at the upper and lower tails of threshold voltage distributions, leading to unsuccessful data retrieval.

Innovation Solution

The system identifies and adjusts the threshold voltages of error-prone memory cells by reducing those in the upper tails and increasing those in the lower tails to move them closer to the center of their respective distributions, thereby reducing errors and improving data read success.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are used to store data, then storage capacity is achieved, but error rates increase for cells at the tails of threshold voltage distributions

Engineering Contradiction:
Improvestorage capacityVSAvoiddata read success rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent dynamically adjusts the threshold voltages of memory cells based on their position in the threshold voltage distribution. Cells at the upper tail have their threshold voltages reduced, while cells at the lower tail have their threshold voltages increased, moving them toward the center of the distribution where read errors are minimized. This parameter adjustment resolves the contradiction by maintaining storage capacity while improving reliability for error-prone cells.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If threshold voltages are adjusted to reduce errors, then data read reliability improves, but additional operations and complexity are introduced

Engineering Contradiction:
Improvedata read success rateVSAvoiderror correction mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the memory system automatically identifies and corrects its own errors through iterative reading and threshold voltage adjustment. The system reads data, identifies cells at the tails of the threshold voltage distribution, adjusts their threshold voltages, and re-reads to verify correction. This self-correcting mechanism improves reliability while keeping the complexity manageable by using the existing memory infrastructure for error correction.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If iterative reading and correction is performed, then data accuracy improves, but reading time increases

Engineering Contradiction:
Improvedata accuracyVSAvoiddata retrieval time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by adjusting threshold voltages of error-prone cells before final data retrieval. By proactively identifying and correcting errors in the first iteration and adjusting threshold voltages, the system reduces the likelihood of requiring multiple correction cycles, thereby improving data accuracy while minimizing the time penalty associated with iterative correction.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12592291B2Non-volatile memory with in-place error updating and correction
Publication Date: 2026.03.31 SANDISK TECHNOLOGIES LLC
  • US12592291B2 patent drawing
  • US12592291B2 patent drawing
  • US12592291B2 patent drawing

AI summary

A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.